1; RUN: llc --mtriple=loongarch64 --filetype=obj -mattr=-relax \ 2; RUN: --relocation-model=pic --code-model=medium < %s \ 3; RUN: | llvm-readobj -r - | FileCheck --check-prefixes=CHECK-RELOC,PCALA-RELOC %s 4; RUN: llc --mtriple=loongarch64 --filetype=obj -mattr=+relax \ 5; RUN: --relocation-model=pic --code-model=medium < %s \ 6; RUN: | llvm-readobj -r - | FileCheck --check-prefixes=CHECK-RELOC,RELAX %s 7 8; RUN: llc --mtriple=loongarch64 --filetype=obj -mattr=-relax --enable-tlsdesc \ 9; RUN: --relocation-model=pic --code-model=medium < %s \ 10; RUN: | llvm-readobj -r - | FileCheck --check-prefix=DESC-RELOC %s 11; RUN: llc --mtriple=loongarch64 --filetype=obj -mattr=+relax --enable-tlsdesc \ 12; RUN: --relocation-model=pic --code-model=medium < %s \ 13; RUN: | llvm-readobj -r - | FileCheck --check-prefixes=DESC-RELOC,DESC-RELAX %s 14 15;; Check relocations when disable or enable linker relaxation. 16;; This tests are also able to test for removing relax mask flags 17;; after loongarch-merge-base-offset pass because no relax relocs 18;; are emitted after being optimized by it. 19 20@g_e = external global i32 21@g_i = internal global i32 0 22@g_i1 = internal global i32 1 23@t_un = external thread_local global i32 24@t_ld = external thread_local(localdynamic) global i32 25@t_ie = external thread_local(initialexec) global i32 26@t_le = external thread_local(localexec) global i32 27 28declare void @callee1() nounwind 29declare dso_local void @callee2() nounwind 30declare dso_local void @callee3() nounwind 31 32define ptr @caller() nounwind { 33; RELAX: R_LARCH_ALIGN - 0x1C 34; CHECK-RELOC: R_LARCH_GOT_PC_HI20 g_e 0x0 35; RELAX-NEXT: R_LARCH_RELAX - 0x0 36; CHECK-RELOC-NEXT: R_LARCH_GOT_PC_LO12 g_e 0x0 37; RELAX-NEXT: R_LARCH_RELAX - 0x0 38; PCALA-RELOC: R_LARCH_PCALA_HI20 .bss 0x0 39; RELAX-NEXT: R_LARCH_PCALA_HI20 g_i 0x0 40; PCALA-RELOC: R_LARCH_PCALA_LO12 .bss 0x0 41; RELAX-NEXT: R_LARCH_PCALA_LO12 g_i 0x0 42; CHECK-RELOC: R_LARCH_TLS_GD_PC_HI20 t_un 0x0 43; RELAX-NEXT: R_LARCH_RELAX - 0x0 44; CHECK-RELOC-NEXT: R_LARCH_GOT_PC_LO12 t_un 0x0 45; RELAX-NEXT: R_LARCH_RELAX - 0x0 46; CHECK-RELOC-NEXT: R_LARCH_CALL36 __tls_get_addr 0x0 47; RELAX-NEXT: R_LARCH_RELAX - 0x0 48; DESC-RELOC: R_LARCH_TLS_DESC_PC_HI20 t_un 0x0 49; DESC-RELAX: R_LARCH_RELAX - 0x0 50; DESC-RELOC-NEXT: R_LARCH_TLS_DESC_PC_LO12 t_un 0x0 51; DESC-RELAX-NEXT: R_LARCH_RELAX - 0x0 52; DESC-RELOC-NEXT: R_LARCH_TLS_DESC_LD t_un 0x0 53; DESC-RELAX-NEXT: R_LARCH_RELAX - 0x0 54; DESC-RELOC-NEXT: R_LARCH_TLS_DESC_CALL t_un 0x0 55; DESC-RELAX-NEXT: R_LARCH_RELAX - 0x0 56; CHECK-RELOC-NEXT: R_LARCH_TLS_LD_PC_HI20 t_ld 0x0 57; RELAX-NEXT: R_LARCH_RELAX - 0x0 58; CHECK-RELOC-NEXT: R_LARCH_GOT_PC_LO12 t_ld 0x0 59; RELAX-NEXT: R_LARCH_RELAX - 0x0 60; CHECK-RELOC-NEXT: R_LARCH_CALL36 __tls_get_addr 0x0 61; RELAX-NEXT: R_LARCH_RELAX - 0x0 62; DESC-RELOC-NEXT: R_LARCH_TLS_DESC_PC_HI20 t_ld 0x0 63; DESC-RELAX-NEXT: R_LARCH_RELAX - 0x0 64; DESC-RELOC-NEXT: R_LARCH_TLS_DESC_PC_LO12 t_ld 0x0 65; DESC-RELAX-NEXT: R_LARCH_RELAX - 0x0 66; DESC-RELOC-NEXT: R_LARCH_TLS_DESC_LD t_ld 0x0 67; DESC-RELAX-NEXT: R_LARCH_RELAX - 0x0 68; DESC-RELOC-NEXT: R_LARCH_TLS_DESC_CALL t_ld 0x0 69; DESC-RELAX-NEXT: R_LARCH_RELAX - 0x0 70; CHECK-RELOC-NEXT: R_LARCH_TLS_IE_PC_HI20 t_ie 0x0 71; RELAX-NEXT: R_LARCH_RELAX - 0x0 72; CHECK-RELOC-NEXT: R_LARCH_TLS_IE_PC_LO12 t_ie 0x0 73; RELAX-NEXT: R_LARCH_RELAX - 0x0 74; CHECK-RELOC-NEXT: R_LARCH_TLS_LE_HI20_R t_le 0x0 75; RELAX-NEXT: R_LARCH_RELAX - 0x0 76; CHECK-RELOC-NEXT: R_LARCH_TLS_LE_ADD_R t_le 0x0 77; RELAX-NEXT: R_LARCH_RELAX - 0x0 78; CHECK-RELOC-NEXT: R_LARCH_TLS_LE_LO12_R t_le 0x0 79; RELAX-NEXT: R_LARCH_RELAX - 0x0 80; CHECK-RELOC-NEXT: R_LARCH_CALL36 callee1 0x0 81; RELAX-NEXT: R_LARCH_RELAX - 0x0 82; CHECK-RELOC-NEXT: R_LARCH_CALL36 callee2 0x0 83; RELAX-NEXT: R_LARCH_RELAX - 0x0 84; CHECK-RELOC-NEXT: R_LARCH_CALL36 callee3 0x0 85; RELAX-NEXT: R_LARCH_RELAX - 0x0 86; PCALA-RELOC: R_LARCH_PCALA_HI20 .data 0x0 87; RELAX-NEXT: R_LARCH_PCALA_HI20 g_i1 0x0 88; RELAX-NEXT: R_LARCH_RELAX - 0x0 89; PCALA-RELOC: R_LARCH_PCALA_LO12 .data 0x0 90; RELAX-NEXT: R_LARCH_PCALA_LO12 g_i1 0x0 91; RELAX-NEXT: R_LARCH_RELAX - 0x0 92 %a = load volatile i32, ptr @g_e 93 %b = load volatile i32, ptr @g_i 94 %c = load volatile i32, ptr @t_un 95 %d = load volatile i32, ptr @t_ld 96 %e = load volatile i32, ptr @t_ie 97 %f = load volatile i32, ptr @t_le 98 call i32 @callee1() 99 call i32 @callee2() 100 tail call i32 @callee3() 101 ret ptr @g_i1 102} 103