xref: /llvm-project/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sllwil.ll (revision 83311b2b5d1b9869f9a7b265994394ea898448a2) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
3
4declare <16 x i16> @llvm.loongarch.lasx.xvsllwil.h.b(<32 x i8>, i32)
5
6define <16 x i16> @lasx_xvsllwil_h_b(<32 x i8> %va) nounwind {
7; CHECK-LABEL: lasx_xvsllwil_h_b:
8; CHECK:       # %bb.0: # %entry
9; CHECK-NEXT:    xvsllwil.h.b $xr0, $xr0, 1
10; CHECK-NEXT:    ret
11entry:
12  %res = call <16 x i16> @llvm.loongarch.lasx.xvsllwil.h.b(<32 x i8> %va, i32 1)
13  ret <16 x i16> %res
14}
15
16declare <8 x i32> @llvm.loongarch.lasx.xvsllwil.w.h(<16 x i16>, i32)
17
18define <8 x i32> @lasx_xvsllwil_w_h(<16 x i16> %va) nounwind {
19; CHECK-LABEL: lasx_xvsllwil_w_h:
20; CHECK:       # %bb.0: # %entry
21; CHECK-NEXT:    xvsllwil.w.h $xr0, $xr0, 1
22; CHECK-NEXT:    ret
23entry:
24  %res = call <8 x i32> @llvm.loongarch.lasx.xvsllwil.w.h(<16 x i16> %va, i32 1)
25  ret <8 x i32> %res
26}
27
28declare <4 x i64> @llvm.loongarch.lasx.xvsllwil.d.w(<8 x i32>, i32)
29
30define <4 x i64> @lasx_xvsllwil_d_w(<8 x i32> %va) nounwind {
31; CHECK-LABEL: lasx_xvsllwil_d_w:
32; CHECK:       # %bb.0: # %entry
33; CHECK-NEXT:    xvsllwil.d.w $xr0, $xr0, 1
34; CHECK-NEXT:    ret
35entry:
36  %res = call <4 x i64> @llvm.loongarch.lasx.xvsllwil.d.w(<8 x i32> %va, i32 1)
37  ret <4 x i64> %res
38}
39
40declare <16 x i16> @llvm.loongarch.lasx.xvsllwil.hu.bu(<32 x i8>, i32)
41
42define <16 x i16> @lasx_xvsllwil_hu_bu(<32 x i8> %va) nounwind {
43; CHECK-LABEL: lasx_xvsllwil_hu_bu:
44; CHECK:       # %bb.0: # %entry
45; CHECK-NEXT:    xvsllwil.hu.bu $xr0, $xr0, 1
46; CHECK-NEXT:    ret
47entry:
48  %res = call <16 x i16> @llvm.loongarch.lasx.xvsllwil.hu.bu(<32 x i8> %va, i32 1)
49  ret <16 x i16> %res
50}
51
52declare <8 x i32> @llvm.loongarch.lasx.xvsllwil.wu.hu(<16 x i16>, i32)
53
54define <8 x i32> @lasx_xvsllwil_wu_hu(<16 x i16> %va) nounwind {
55; CHECK-LABEL: lasx_xvsllwil_wu_hu:
56; CHECK:       # %bb.0: # %entry
57; CHECK-NEXT:    xvsllwil.wu.hu $xr0, $xr0, 1
58; CHECK-NEXT:    ret
59entry:
60  %res = call <8 x i32> @llvm.loongarch.lasx.xvsllwil.wu.hu(<16 x i16> %va, i32 1)
61  ret <8 x i32> %res
62}
63
64declare <4 x i64> @llvm.loongarch.lasx.xvsllwil.du.wu(<8 x i32>, i32)
65
66define <4 x i64> @lasx_xvsllwil_du_wu(<8 x i32> %va) nounwind {
67; CHECK-LABEL: lasx_xvsllwil_du_wu:
68; CHECK:       # %bb.0: # %entry
69; CHECK-NEXT:    xvsllwil.du.wu $xr0, $xr0, 1
70; CHECK-NEXT:    ret
71entry:
72  %res = call <4 x i64> @llvm.loongarch.lasx.xvsllwil.du.wu(<8 x i32> %va, i32 1)
73  ret <4 x i64> %res
74}
75