1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s 3 4 5 6 7declare i32 @llvm.loongarch.lasx.xvpickve2gr.w(<8 x i32>, i32) 8 9define i32 @lasx_xvpickve2gr_w(<8 x i32> %va) nounwind { 10; CHECK-LABEL: lasx_xvpickve2gr_w: 11; CHECK: # %bb.0: # %entry 12; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 1 13; CHECK-NEXT: ret 14entry: 15 %res = call i32 @llvm.loongarch.lasx.xvpickve2gr.w(<8 x i32> %va, i32 1) 16 ret i32 %res 17} 18 19declare i64 @llvm.loongarch.lasx.xvpickve2gr.d(<4 x i64>, i32) 20 21define i64 @lasx_xvpickve2gr_d(<4 x i64> %va) nounwind { 22; CHECK-LABEL: lasx_xvpickve2gr_d: 23; CHECK: # %bb.0: # %entry 24; CHECK-NEXT: xvpickve2gr.d $a0, $xr0, 1 25; CHECK-NEXT: ret 26entry: 27 %res = call i64 @llvm.loongarch.lasx.xvpickve2gr.d(<4 x i64> %va, i32 1) 28 ret i64 %res 29} 30 31declare i32 @llvm.loongarch.lasx.xvpickve2gr.wu(<8 x i32>, i32) 32 33define i32 @lasx_xvpickve2gr_wu(<8 x i32> %va) nounwind { 34; CHECK-LABEL: lasx_xvpickve2gr_wu: 35; CHECK: # %bb.0: # %entry 36; CHECK-NEXT: xvpickve2gr.wu $a0, $xr0, 1 37; CHECK-NEXT: ret 38entry: 39 %res = call i32 @llvm.loongarch.lasx.xvpickve2gr.wu(<8 x i32> %va, i32 1) 40 ret i32 %res 41} 42 43declare i64 @llvm.loongarch.lasx.xvpickve2gr.du(<4 x i64>, i32) 44 45define i64 @lasx_xvpickve2gr_du(<4 x i64> %va) nounwind { 46; CHECK-LABEL: lasx_xvpickve2gr_du: 47; CHECK: # %bb.0: # %entry 48; CHECK-NEXT: xvpickve2gr.du $a0, $xr0, 1 49; CHECK-NEXT: ret 50entry: 51 %res = call i64 @llvm.loongarch.lasx.xvpickve2gr.du(<4 x i64> %va, i32 1) 52 ret i64 %res 53} 54