1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s 3 4declare <8 x i32> @llvm.loongarch.lasx.xvinsgr2vr.w(<8 x i32>, i32, i32) 5 6define <8 x i32> @lasx_xvinsgr2vr_w(<8 x i32> %va) nounwind { 7; CHECK-LABEL: lasx_xvinsgr2vr_w: 8; CHECK: # %bb.0: # %entry 9; CHECK-NEXT: ori $a0, $zero, 1 10; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 1 11; CHECK-NEXT: ret 12entry: 13 %res = call <8 x i32> @llvm.loongarch.lasx.xvinsgr2vr.w(<8 x i32> %va, i32 1, i32 1) 14 ret <8 x i32> %res 15} 16 17declare <4 x i64> @llvm.loongarch.lasx.xvinsgr2vr.d(<4 x i64>, i64, i32) 18 19define <4 x i64> @lasx_xvinsgr2vr_d(<4 x i64> %va) nounwind { 20; CHECK-LABEL: lasx_xvinsgr2vr_d: 21; CHECK: # %bb.0: # %entry 22; CHECK-NEXT: ori $a0, $zero, 1 23; CHECK-NEXT: xvinsgr2vr.d $xr0, $a0, 1 24; CHECK-NEXT: ret 25entry: 26 %res = call <4 x i64> @llvm.loongarch.lasx.xvinsgr2vr.d(<4 x i64> %va, i64 1, i32 1) 27 ret <4 x i64> %res 28} 29