xref: /llvm-project/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ext2xv.ll (revision 83311b2b5d1b9869f9a7b265994394ea898448a2) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
3
4declare <16 x i16> @llvm.loongarch.lasx.vext2xv.h.b(<32 x i8>)
5
6define <16 x i16> @lasx_vext2xv_h_b(<32 x i8> %va) nounwind {
7; CHECK-LABEL: lasx_vext2xv_h_b:
8; CHECK:       # %bb.0: # %entry
9; CHECK-NEXT:    vext2xv.h.b $xr0, $xr0
10; CHECK-NEXT:    ret
11entry:
12  %res = call <16 x i16> @llvm.loongarch.lasx.vext2xv.h.b(<32 x i8> %va)
13  ret <16 x i16> %res
14}
15
16declare <8 x i32> @llvm.loongarch.lasx.vext2xv.w.b(<32 x i8>)
17
18define <8 x i32> @lasx_vext2xv_w_b(<32 x i8> %va) nounwind {
19; CHECK-LABEL: lasx_vext2xv_w_b:
20; CHECK:       # %bb.0: # %entry
21; CHECK-NEXT:    vext2xv.w.b $xr0, $xr0
22; CHECK-NEXT:    ret
23entry:
24  %res = call <8 x i32> @llvm.loongarch.lasx.vext2xv.w.b(<32 x i8> %va)
25  ret <8 x i32> %res
26}
27
28declare <4 x i64> @llvm.loongarch.lasx.vext2xv.d.b(<32 x i8>)
29
30define <4 x i64> @lasx_vext2xv_d_b(<32 x i8> %va) nounwind {
31; CHECK-LABEL: lasx_vext2xv_d_b:
32; CHECK:       # %bb.0: # %entry
33; CHECK-NEXT:    vext2xv.d.b $xr0, $xr0
34; CHECK-NEXT:    ret
35entry:
36  %res = call <4 x i64> @llvm.loongarch.lasx.vext2xv.d.b(<32 x i8> %va)
37  ret <4 x i64> %res
38}
39
40declare <8 x i32> @llvm.loongarch.lasx.vext2xv.w.h(<16 x i16>)
41
42define <8 x i32> @lasx_vext2xv_w_h(<16 x i16> %va) nounwind {
43; CHECK-LABEL: lasx_vext2xv_w_h:
44; CHECK:       # %bb.0: # %entry
45; CHECK-NEXT:    vext2xv.w.h $xr0, $xr0
46; CHECK-NEXT:    ret
47entry:
48  %res = call <8 x i32> @llvm.loongarch.lasx.vext2xv.w.h(<16 x i16> %va)
49  ret <8 x i32> %res
50}
51
52declare <4 x i64> @llvm.loongarch.lasx.vext2xv.d.h(<16 x i16>)
53
54define <4 x i64> @lasx_vext2xv_d_h(<16 x i16> %va) nounwind {
55; CHECK-LABEL: lasx_vext2xv_d_h:
56; CHECK:       # %bb.0: # %entry
57; CHECK-NEXT:    vext2xv.d.h $xr0, $xr0
58; CHECK-NEXT:    ret
59entry:
60  %res = call <4 x i64> @llvm.loongarch.lasx.vext2xv.d.h(<16 x i16> %va)
61  ret <4 x i64> %res
62}
63
64declare <4 x i64> @llvm.loongarch.lasx.vext2xv.d.w(<8 x i32>)
65
66define <4 x i64> @lasx_vext2xv_d_w(<8 x i32> %va) nounwind {
67; CHECK-LABEL: lasx_vext2xv_d_w:
68; CHECK:       # %bb.0: # %entry
69; CHECK-NEXT:    vext2xv.d.w $xr0, $xr0
70; CHECK-NEXT:    ret
71entry:
72  %res = call <4 x i64> @llvm.loongarch.lasx.vext2xv.d.w(<8 x i32> %va)
73  ret <4 x i64> %res
74}
75
76declare <16 x i16> @llvm.loongarch.lasx.vext2xv.hu.bu(<32 x i8>)
77
78define <16 x i16> @lasx_vext2xv_hu_bu(<32 x i8> %va) nounwind {
79; CHECK-LABEL: lasx_vext2xv_hu_bu:
80; CHECK:       # %bb.0: # %entry
81; CHECK-NEXT:    vext2xv.hu.bu $xr0, $xr0
82; CHECK-NEXT:    ret
83entry:
84  %res = call <16 x i16> @llvm.loongarch.lasx.vext2xv.hu.bu(<32 x i8> %va)
85  ret <16 x i16> %res
86}
87
88declare <8 x i32> @llvm.loongarch.lasx.vext2xv.wu.bu(<32 x i8>)
89
90define <8 x i32> @lasx_vext2xv_wu_bu(<32 x i8> %va) nounwind {
91; CHECK-LABEL: lasx_vext2xv_wu_bu:
92; CHECK:       # %bb.0: # %entry
93; CHECK-NEXT:    vext2xv.wu.bu $xr0, $xr0
94; CHECK-NEXT:    ret
95entry:
96  %res = call <8 x i32> @llvm.loongarch.lasx.vext2xv.wu.bu(<32 x i8> %va)
97  ret <8 x i32> %res
98}
99
100declare <4 x i64> @llvm.loongarch.lasx.vext2xv.du.bu(<32 x i8>)
101
102define <4 x i64> @lasx_vext2xv_du_bu(<32 x i8> %va) nounwind {
103; CHECK-LABEL: lasx_vext2xv_du_bu:
104; CHECK:       # %bb.0: # %entry
105; CHECK-NEXT:    vext2xv.du.bu $xr0, $xr0
106; CHECK-NEXT:    ret
107entry:
108  %res = call <4 x i64> @llvm.loongarch.lasx.vext2xv.du.bu(<32 x i8> %va)
109  ret <4 x i64> %res
110}
111
112declare <8 x i32> @llvm.loongarch.lasx.vext2xv.wu.hu(<16 x i16>)
113
114define <8 x i32> @lasx_vext2xv_wu_hu(<16 x i16> %va) nounwind {
115; CHECK-LABEL: lasx_vext2xv_wu_hu:
116; CHECK:       # %bb.0: # %entry
117; CHECK-NEXT:    vext2xv.wu.hu $xr0, $xr0
118; CHECK-NEXT:    ret
119entry:
120  %res = call <8 x i32> @llvm.loongarch.lasx.vext2xv.wu.hu(<16 x i16> %va)
121  ret <8 x i32> %res
122}
123
124declare <4 x i64> @llvm.loongarch.lasx.vext2xv.du.hu(<16 x i16>)
125
126define <4 x i64> @lasx_vext2xv_du_hu(<16 x i16> %va) nounwind {
127; CHECK-LABEL: lasx_vext2xv_du_hu:
128; CHECK:       # %bb.0: # %entry
129; CHECK-NEXT:    vext2xv.du.hu $xr0, $xr0
130; CHECK-NEXT:    ret
131entry:
132  %res = call <4 x i64> @llvm.loongarch.lasx.vext2xv.du.hu(<16 x i16> %va)
133  ret <4 x i64> %res
134}
135
136declare <4 x i64> @llvm.loongarch.lasx.vext2xv.du.wu(<8 x i32>)
137
138define <4 x i64> @lasx_vext2xv_du_wu(<8 x i32> %va) nounwind {
139; CHECK-LABEL: lasx_vext2xv_du_wu:
140; CHECK:       # %bb.0: # %entry
141; CHECK-NEXT:    vext2xv.du.wu $xr0, $xr0
142; CHECK-NEXT:    ret
143entry:
144  %res = call <4 x i64> @llvm.loongarch.lasx.vext2xv.du.wu(<8 x i32> %va)
145  ret <4 x i64> %res
146}
147