xref: /llvm-project/llvm/test/CodeGen/LoongArch/is_fpclass_f64.ll (revision 0a692b6b9632e1460f9e0e983196f2be5879acd1) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
2; RUN: llc --mtriple=loongarch32 --mattr=+d --verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK32
3; RUN: llc --mtriple=loongarch64 --mattr=+d --verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK64
4
5define i1 @isnan_d(double %x) {
6; CHECK32-LABEL: isnan_d:
7; CHECK32:       # %bb.0: # %entry
8; CHECK32-NEXT:    fclass.d $fa0, $fa0
9; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
10; CHECK32-NEXT:    andi $a0, $a0, 3
11; CHECK32-NEXT:    sltu $a0, $zero, $a0
12; CHECK32-NEXT:    ret
13;
14; CHECK64-LABEL: isnan_d:
15; CHECK64:       # %bb.0: # %entry
16; CHECK64-NEXT:    fclass.d $fa0, $fa0
17; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
18; CHECK64-NEXT:    andi $a0, $a0, 3
19; CHECK64-NEXT:    sltu $a0, $zero, $a0
20; CHECK64-NEXT:    ret
21entry:
22  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 3)  ; "nan"
23  ret i1 %0
24}
25
26define i1 @isnot_nan_d(double %x) {
27; CHECK32-LABEL: isnot_nan_d:
28; CHECK32:       # %bb.0: # %entry
29; CHECK32-NEXT:    fclass.d $fa0, $fa0
30; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
31; CHECK32-NEXT:    andi $a0, $a0, 1020
32; CHECK32-NEXT:    sltu $a0, $zero, $a0
33; CHECK32-NEXT:    ret
34;
35; CHECK64-LABEL: isnot_nan_d:
36; CHECK64:       # %bb.0: # %entry
37; CHECK64-NEXT:    fclass.d $fa0, $fa0
38; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
39; CHECK64-NEXT:    andi $a0, $a0, 1020
40; CHECK64-NEXT:    sltu $a0, $zero, $a0
41; CHECK64-NEXT:    ret
42entry:
43  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 1020)  ; 0x3fc = "zero|subnormal|normal|inf"
44  ret i1 %0
45}
46
47define i1 @issignaling_d(double %x) {
48; CHECK32-LABEL: issignaling_d:
49; CHECK32:       # %bb.0: # %entry
50; CHECK32-NEXT:    fclass.d $fa0, $fa0
51; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
52; CHECK32-NEXT:    andi $a0, $a0, 1
53; CHECK32-NEXT:    sltu $a0, $zero, $a0
54; CHECK32-NEXT:    ret
55;
56; CHECK64-LABEL: issignaling_d:
57; CHECK64:       # %bb.0: # %entry
58; CHECK64-NEXT:    fclass.d $fa0, $fa0
59; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
60; CHECK64-NEXT:    andi $a0, $a0, 1
61; CHECK64-NEXT:    sltu $a0, $zero, $a0
62; CHECK64-NEXT:    ret
63entry:
64  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 1)  ; "snan"
65  ret i1 %0
66}
67
68define i1 @not_issignaling_d(double %x) {
69; CHECK32-LABEL: not_issignaling_d:
70; CHECK32:       # %bb.0: # %entry
71; CHECK32-NEXT:    fclass.d $fa0, $fa0
72; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
73; CHECK32-NEXT:    andi $a0, $a0, 1022
74; CHECK32-NEXT:    sltu $a0, $zero, $a0
75; CHECK32-NEXT:    ret
76;
77; CHECK64-LABEL: not_issignaling_d:
78; CHECK64:       # %bb.0: # %entry
79; CHECK64-NEXT:    fclass.d $fa0, $fa0
80; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
81; CHECK64-NEXT:    andi $a0, $a0, 1022
82; CHECK64-NEXT:    sltu $a0, $zero, $a0
83; CHECK64-NEXT:    ret
84entry:
85  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 1022)  ; ~"snan"
86  ret i1 %0
87}
88
89define i1 @isquiet_d(double %x) {
90; CHECK32-LABEL: isquiet_d:
91; CHECK32:       # %bb.0: # %entry
92; CHECK32-NEXT:    fclass.d $fa0, $fa0
93; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
94; CHECK32-NEXT:    andi $a0, $a0, 2
95; CHECK32-NEXT:    sltu $a0, $zero, $a0
96; CHECK32-NEXT:    ret
97;
98; CHECK64-LABEL: isquiet_d:
99; CHECK64:       # %bb.0: # %entry
100; CHECK64-NEXT:    fclass.d $fa0, $fa0
101; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
102; CHECK64-NEXT:    andi $a0, $a0, 2
103; CHECK64-NEXT:    sltu $a0, $zero, $a0
104; CHECK64-NEXT:    ret
105entry:
106  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 2)  ; "qnan"
107  ret i1 %0
108}
109
110define i1 @not_isquiet_d(double %x) {
111; CHECK32-LABEL: not_isquiet_d:
112; CHECK32:       # %bb.0: # %entry
113; CHECK32-NEXT:    fclass.d $fa0, $fa0
114; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
115; CHECK32-NEXT:    andi $a0, $a0, 1021
116; CHECK32-NEXT:    sltu $a0, $zero, $a0
117; CHECK32-NEXT:    ret
118;
119; CHECK64-LABEL: not_isquiet_d:
120; CHECK64:       # %bb.0: # %entry
121; CHECK64-NEXT:    fclass.d $fa0, $fa0
122; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
123; CHECK64-NEXT:    andi $a0, $a0, 1021
124; CHECK64-NEXT:    sltu $a0, $zero, $a0
125; CHECK64-NEXT:    ret
126entry:
127  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 1021)  ; ~"qnan"
128  ret i1 %0
129}
130
131define i1 @isinf_d(double %x) {
132; CHECK32-LABEL: isinf_d:
133; CHECK32:       # %bb.0: # %entry
134; CHECK32-NEXT:    fclass.d $fa0, $fa0
135; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
136; CHECK32-NEXT:    andi $a0, $a0, 68
137; CHECK32-NEXT:    sltu $a0, $zero, $a0
138; CHECK32-NEXT:    ret
139;
140; CHECK64-LABEL: isinf_d:
141; CHECK64:       # %bb.0: # %entry
142; CHECK64-NEXT:    fclass.d $fa0, $fa0
143; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
144; CHECK64-NEXT:    andi $a0, $a0, 68
145; CHECK64-NEXT:    sltu $a0, $zero, $a0
146; CHECK64-NEXT:    ret
147entry:
148  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 516)  ; 0x204 = "inf"
149  ret i1 %0
150}
151
152define i1 @not_isinf_d(double %x) {
153; CHECK32-LABEL: not_isinf_d:
154; CHECK32:       # %bb.0: # %entry
155; CHECK32-NEXT:    fclass.d $fa0, $fa0
156; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
157; CHECK32-NEXT:    andi $a0, $a0, 955
158; CHECK32-NEXT:    sltu $a0, $zero, $a0
159; CHECK32-NEXT:    ret
160;
161; CHECK64-LABEL: not_isinf_d:
162; CHECK64:       # %bb.0: # %entry
163; CHECK64-NEXT:    fclass.d $fa0, $fa0
164; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
165; CHECK64-NEXT:    andi $a0, $a0, 955
166; CHECK64-NEXT:    sltu $a0, $zero, $a0
167; CHECK64-NEXT:    ret
168entry:
169  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 507)  ; ~0x204 = "~inf"
170  ret i1 %0
171}
172
173define i1 @is_plus_inf_d(double %x) {
174; CHECK32-LABEL: is_plus_inf_d:
175; CHECK32:       # %bb.0: # %entry
176; CHECK32-NEXT:    fclass.d $fa0, $fa0
177; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
178; CHECK32-NEXT:    andi $a0, $a0, 64
179; CHECK32-NEXT:    sltu $a0, $zero, $a0
180; CHECK32-NEXT:    ret
181;
182; CHECK64-LABEL: is_plus_inf_d:
183; CHECK64:       # %bb.0: # %entry
184; CHECK64-NEXT:    fclass.d $fa0, $fa0
185; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
186; CHECK64-NEXT:    andi $a0, $a0, 64
187; CHECK64-NEXT:    sltu $a0, $zero, $a0
188; CHECK64-NEXT:    ret
189entry:
190  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 512)  ; 0x200 = "+inf"
191  ret i1 %0
192}
193
194define i1 @is_minus_inf_d(double %x) {
195; CHECK32-LABEL: is_minus_inf_d:
196; CHECK32:       # %bb.0: # %entry
197; CHECK32-NEXT:    fclass.d $fa0, $fa0
198; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
199; CHECK32-NEXT:    andi $a0, $a0, 4
200; CHECK32-NEXT:    sltu $a0, $zero, $a0
201; CHECK32-NEXT:    ret
202;
203; CHECK64-LABEL: is_minus_inf_d:
204; CHECK64:       # %bb.0: # %entry
205; CHECK64-NEXT:    fclass.d $fa0, $fa0
206; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
207; CHECK64-NEXT:    andi $a0, $a0, 4
208; CHECK64-NEXT:    sltu $a0, $zero, $a0
209; CHECK64-NEXT:    ret
210entry:
211  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 4)  ; "-inf"
212  ret i1 %0
213}
214
215define i1 @not_is_minus_inf_d(double %x) {
216; CHECK32-LABEL: not_is_minus_inf_d:
217; CHECK32:       # %bb.0: # %entry
218; CHECK32-NEXT:    fclass.d $fa0, $fa0
219; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
220; CHECK32-NEXT:    andi $a0, $a0, 1019
221; CHECK32-NEXT:    sltu $a0, $zero, $a0
222; CHECK32-NEXT:    ret
223;
224; CHECK64-LABEL: not_is_minus_inf_d:
225; CHECK64:       # %bb.0: # %entry
226; CHECK64-NEXT:    fclass.d $fa0, $fa0
227; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
228; CHECK64-NEXT:    andi $a0, $a0, 1019
229; CHECK64-NEXT:    sltu $a0, $zero, $a0
230; CHECK64-NEXT:    ret
231entry:
232  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 1019)  ; ~"-inf"
233  ret i1 %0
234}
235
236define i1 @isfinite_d(double %x) {
237; CHECK32-LABEL: isfinite_d:
238; CHECK32:       # %bb.0: # %entry
239; CHECK32-NEXT:    fclass.d $fa0, $fa0
240; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
241; CHECK32-NEXT:    andi $a0, $a0, 952
242; CHECK32-NEXT:    sltu $a0, $zero, $a0
243; CHECK32-NEXT:    ret
244;
245; CHECK64-LABEL: isfinite_d:
246; CHECK64:       # %bb.0: # %entry
247; CHECK64-NEXT:    fclass.d $fa0, $fa0
248; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
249; CHECK64-NEXT:    andi $a0, $a0, 952
250; CHECK64-NEXT:    sltu $a0, $zero, $a0
251; CHECK64-NEXT:    ret
252entry:
253  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 504)  ; 0x1f8 = "finite"
254  ret i1 %0
255}
256
257define i1 @not_isfinite_d(double %x) {
258; CHECK32-LABEL: not_isfinite_d:
259; CHECK32:       # %bb.0: # %entry
260; CHECK32-NEXT:    fclass.d $fa0, $fa0
261; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
262; CHECK32-NEXT:    andi $a0, $a0, 71
263; CHECK32-NEXT:    sltu $a0, $zero, $a0
264; CHECK32-NEXT:    ret
265;
266; CHECK64-LABEL: not_isfinite_d:
267; CHECK64:       # %bb.0: # %entry
268; CHECK64-NEXT:    fclass.d $fa0, $fa0
269; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
270; CHECK64-NEXT:    andi $a0, $a0, 71
271; CHECK64-NEXT:    sltu $a0, $zero, $a0
272; CHECK64-NEXT:    ret
273entry:
274  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 519)  ; ~0x1f8 = "~finite"
275  ret i1 %0
276}
277
278define i1 @is_plus_finite_d(double %x) {
279; CHECK32-LABEL: is_plus_finite_d:
280; CHECK32:       # %bb.0: # %entry
281; CHECK32-NEXT:    fclass.d $fa0, $fa0
282; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
283; CHECK32-NEXT:    andi $a0, $a0, 896
284; CHECK32-NEXT:    sltu $a0, $zero, $a0
285; CHECK32-NEXT:    ret
286;
287; CHECK64-LABEL: is_plus_finite_d:
288; CHECK64:       # %bb.0: # %entry
289; CHECK64-NEXT:    fclass.d $fa0, $fa0
290; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
291; CHECK64-NEXT:    andi $a0, $a0, 896
292; CHECK64-NEXT:    sltu $a0, $zero, $a0
293; CHECK64-NEXT:    ret
294entry:
295  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 448)  ; 0x1c0 = "+finite"
296  ret i1 %0
297}
298
299define i1 @not_is_plus_finite_d(double %x) {
300; CHECK32-LABEL: not_is_plus_finite_d:
301; CHECK32:       # %bb.0: # %entry
302; CHECK32-NEXT:    fclass.d $fa0, $fa0
303; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
304; CHECK32-NEXT:    andi $a0, $a0, 127
305; CHECK32-NEXT:    sltu $a0, $zero, $a0
306; CHECK32-NEXT:    ret
307;
308; CHECK64-LABEL: not_is_plus_finite_d:
309; CHECK64:       # %bb.0: # %entry
310; CHECK64-NEXT:    fclass.d $fa0, $fa0
311; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
312; CHECK64-NEXT:    andi $a0, $a0, 127
313; CHECK64-NEXT:    sltu $a0, $zero, $a0
314; CHECK64-NEXT:    ret
315entry:
316  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 575)  ; ~0x1c0 = ~"+finite"
317  ret i1 %0
318}
319
320define i1 @is_minus_finite_d(double %x) {
321; CHECK32-LABEL: is_minus_finite_d:
322; CHECK32:       # %bb.0: # %entry
323; CHECK32-NEXT:    fclass.d $fa0, $fa0
324; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
325; CHECK32-NEXT:    andi $a0, $a0, 56
326; CHECK32-NEXT:    sltu $a0, $zero, $a0
327; CHECK32-NEXT:    ret
328;
329; CHECK64-LABEL: is_minus_finite_d:
330; CHECK64:       # %bb.0: # %entry
331; CHECK64-NEXT:    fclass.d $fa0, $fa0
332; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
333; CHECK64-NEXT:    andi $a0, $a0, 56
334; CHECK64-NEXT:    sltu $a0, $zero, $a0
335; CHECK64-NEXT:    ret
336entry:
337  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 56)  ; 0x38 = "-finite"
338  ret i1 %0
339}
340
341define i1 @not_is_minus_finite_d(double %x) {
342; CHECK32-LABEL: not_is_minus_finite_d:
343; CHECK32:       # %bb.0: # %entry
344; CHECK32-NEXT:    fclass.d $fa0, $fa0
345; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
346; CHECK32-NEXT:    andi $a0, $a0, 967
347; CHECK32-NEXT:    sltu $a0, $zero, $a0
348; CHECK32-NEXT:    ret
349;
350; CHECK64-LABEL: not_is_minus_finite_d:
351; CHECK64:       # %bb.0: # %entry
352; CHECK64-NEXT:    fclass.d $fa0, $fa0
353; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
354; CHECK64-NEXT:    andi $a0, $a0, 967
355; CHECK64-NEXT:    sltu $a0, $zero, $a0
356; CHECK64-NEXT:    ret
357entry:
358  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 967)  ; ~0x38 = ~"-finite"
359  ret i1 %0
360}
361
362define i1 @isnormal_d(double %x) {
363; CHECK32-LABEL: isnormal_d:
364; CHECK32:       # %bb.0: # %entry
365; CHECK32-NEXT:    fclass.d $fa0, $fa0
366; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
367; CHECK32-NEXT:    andi $a0, $a0, 136
368; CHECK32-NEXT:    sltu $a0, $zero, $a0
369; CHECK32-NEXT:    ret
370;
371; CHECK64-LABEL: isnormal_d:
372; CHECK64:       # %bb.0: # %entry
373; CHECK64-NEXT:    fclass.d $fa0, $fa0
374; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
375; CHECK64-NEXT:    andi $a0, $a0, 136
376; CHECK64-NEXT:    sltu $a0, $zero, $a0
377; CHECK64-NEXT:    ret
378entry:
379  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 264)  ; 0x108 = "normal"
380  ret i1 %0
381}
382
383define i1 @not_isnormal_d(double %x) {
384; CHECK32-LABEL: not_isnormal_d:
385; CHECK32:       # %bb.0: # %entry
386; CHECK32-NEXT:    fclass.d $fa0, $fa0
387; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
388; CHECK32-NEXT:    andi $a0, $a0, 887
389; CHECK32-NEXT:    sltu $a0, $zero, $a0
390; CHECK32-NEXT:    ret
391;
392; CHECK64-LABEL: not_isnormal_d:
393; CHECK64:       # %bb.0: # %entry
394; CHECK64-NEXT:    fclass.d $fa0, $fa0
395; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
396; CHECK64-NEXT:    andi $a0, $a0, 887
397; CHECK64-NEXT:    sltu $a0, $zero, $a0
398; CHECK64-NEXT:    ret
399entry:
400  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 759)  ; ~0x108 = "~normal"
401  ret i1 %0
402}
403
404define i1 @is_plus_normal_d(double %x) {
405; CHECK32-LABEL: is_plus_normal_d:
406; CHECK32:       # %bb.0: # %entry
407; CHECK32-NEXT:    fclass.d $fa0, $fa0
408; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
409; CHECK32-NEXT:    andi $a0, $a0, 128
410; CHECK32-NEXT:    sltu $a0, $zero, $a0
411; CHECK32-NEXT:    ret
412;
413; CHECK64-LABEL: is_plus_normal_d:
414; CHECK64:       # %bb.0: # %entry
415; CHECK64-NEXT:    fclass.d $fa0, $fa0
416; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
417; CHECK64-NEXT:    andi $a0, $a0, 128
418; CHECK64-NEXT:    sltu $a0, $zero, $a0
419; CHECK64-NEXT:    ret
420entry:
421  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 256)  ; 0x100 = "+normal"
422  ret i1 %0
423}
424
425define i1 @issubnormal_d(double %x) {
426; CHECK32-LABEL: issubnormal_d:
427; CHECK32:       # %bb.0: # %entry
428; CHECK32-NEXT:    fclass.d $fa0, $fa0
429; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
430; CHECK32-NEXT:    andi $a0, $a0, 272
431; CHECK32-NEXT:    sltu $a0, $zero, $a0
432; CHECK32-NEXT:    ret
433;
434; CHECK64-LABEL: issubnormal_d:
435; CHECK64:       # %bb.0: # %entry
436; CHECK64-NEXT:    fclass.d $fa0, $fa0
437; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
438; CHECK64-NEXT:    andi $a0, $a0, 272
439; CHECK64-NEXT:    sltu $a0, $zero, $a0
440; CHECK64-NEXT:    ret
441entry:
442  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 144)  ; 0x90 = "subnormal"
443  ret i1 %0
444}
445
446define i1 @not_issubnormal_d(double %x) {
447; CHECK32-LABEL: not_issubnormal_d:
448; CHECK32:       # %bb.0: # %entry
449; CHECK32-NEXT:    fclass.d $fa0, $fa0
450; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
451; CHECK32-NEXT:    andi $a0, $a0, 751
452; CHECK32-NEXT:    sltu $a0, $zero, $a0
453; CHECK32-NEXT:    ret
454;
455; CHECK64-LABEL: not_issubnormal_d:
456; CHECK64:       # %bb.0: # %entry
457; CHECK64-NEXT:    fclass.d $fa0, $fa0
458; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
459; CHECK64-NEXT:    andi $a0, $a0, 751
460; CHECK64-NEXT:    sltu $a0, $zero, $a0
461; CHECK64-NEXT:    ret
462entry:
463  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 879)  ; ~0x90 = "~subnormal"
464  ret i1 %0
465}
466
467define i1 @is_plus_subnormal_d(double %x) {
468; CHECK32-LABEL: is_plus_subnormal_d:
469; CHECK32:       # %bb.0: # %entry
470; CHECK32-NEXT:    fclass.d $fa0, $fa0
471; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
472; CHECK32-NEXT:    andi $a0, $a0, 256
473; CHECK32-NEXT:    sltu $a0, $zero, $a0
474; CHECK32-NEXT:    ret
475;
476; CHECK64-LABEL: is_plus_subnormal_d:
477; CHECK64:       # %bb.0: # %entry
478; CHECK64-NEXT:    fclass.d $fa0, $fa0
479; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
480; CHECK64-NEXT:    andi $a0, $a0, 256
481; CHECK64-NEXT:    sltu $a0, $zero, $a0
482; CHECK64-NEXT:    ret
483entry:
484  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 128)  ; 0x80 = "+subnormal"
485  ret i1 %0
486}
487
488define i1 @not_is_plus_subnormal_d(double %x) {
489; CHECK32-LABEL: not_is_plus_subnormal_d:
490; CHECK32:       # %bb.0: # %entry
491; CHECK32-NEXT:    fclass.d $fa0, $fa0
492; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
493; CHECK32-NEXT:    andi $a0, $a0, 767
494; CHECK32-NEXT:    sltu $a0, $zero, $a0
495; CHECK32-NEXT:    ret
496;
497; CHECK64-LABEL: not_is_plus_subnormal_d:
498; CHECK64:       # %bb.0: # %entry
499; CHECK64-NEXT:    fclass.d $fa0, $fa0
500; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
501; CHECK64-NEXT:    andi $a0, $a0, 767
502; CHECK64-NEXT:    sltu $a0, $zero, $a0
503; CHECK64-NEXT:    ret
504entry:
505  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 895)  ; ~0x80 = ~"+subnormal"
506  ret i1 %0
507}
508
509define i1 @is_minus_subnormal_d(double %x) {
510; CHECK32-LABEL: is_minus_subnormal_d:
511; CHECK32:       # %bb.0: # %entry
512; CHECK32-NEXT:    fclass.d $fa0, $fa0
513; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
514; CHECK32-NEXT:    andi $a0, $a0, 16
515; CHECK32-NEXT:    sltu $a0, $zero, $a0
516; CHECK32-NEXT:    ret
517;
518; CHECK64-LABEL: is_minus_subnormal_d:
519; CHECK64:       # %bb.0: # %entry
520; CHECK64-NEXT:    fclass.d $fa0, $fa0
521; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
522; CHECK64-NEXT:    andi $a0, $a0, 16
523; CHECK64-NEXT:    sltu $a0, $zero, $a0
524; CHECK64-NEXT:    ret
525entry:
526  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 16)  ; 0x10 = "-subnormal"
527  ret i1 %0
528}
529
530define i1 @not_is_minus_subnormal_d(double %x) {
531; CHECK32-LABEL: not_is_minus_subnormal_d:
532; CHECK32:       # %bb.0: # %entry
533; CHECK32-NEXT:    fclass.d $fa0, $fa0
534; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
535; CHECK32-NEXT:    andi $a0, $a0, 1007
536; CHECK32-NEXT:    sltu $a0, $zero, $a0
537; CHECK32-NEXT:    ret
538;
539; CHECK64-LABEL: not_is_minus_subnormal_d:
540; CHECK64:       # %bb.0: # %entry
541; CHECK64-NEXT:    fclass.d $fa0, $fa0
542; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
543; CHECK64-NEXT:    andi $a0, $a0, 1007
544; CHECK64-NEXT:    sltu $a0, $zero, $a0
545; CHECK64-NEXT:    ret
546entry:
547  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 1007)  ; ~0x10 = ~"-subnormal"
548  ret i1 %0
549}
550
551define i1 @iszero_d(double %x) {
552; CHECK32-LABEL: iszero_d:
553; CHECK32:       # %bb.0: # %entry
554; CHECK32-NEXT:    fclass.d $fa0, $fa0
555; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
556; CHECK32-NEXT:    andi $a0, $a0, 544
557; CHECK32-NEXT:    sltu $a0, $zero, $a0
558; CHECK32-NEXT:    ret
559;
560; CHECK64-LABEL: iszero_d:
561; CHECK64:       # %bb.0: # %entry
562; CHECK64-NEXT:    fclass.d $fa0, $fa0
563; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
564; CHECK64-NEXT:    andi $a0, $a0, 544
565; CHECK64-NEXT:    sltu $a0, $zero, $a0
566; CHECK64-NEXT:    ret
567entry:
568  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 96)  ; 0x60 = "zero"
569  ret i1 %0
570}
571
572define i1 @not_iszero_d(double %x) {
573; CHECK32-LABEL: not_iszero_d:
574; CHECK32:       # %bb.0: # %entry
575; CHECK32-NEXT:    fclass.d $fa0, $fa0
576; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
577; CHECK32-NEXT:    andi $a0, $a0, 479
578; CHECK32-NEXT:    sltu $a0, $zero, $a0
579; CHECK32-NEXT:    ret
580;
581; CHECK64-LABEL: not_iszero_d:
582; CHECK64:       # %bb.0: # %entry
583; CHECK64-NEXT:    fclass.d $fa0, $fa0
584; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
585; CHECK64-NEXT:    andi $a0, $a0, 479
586; CHECK64-NEXT:    sltu $a0, $zero, $a0
587; CHECK64-NEXT:    ret
588entry:
589  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 927)  ; ~0x60 = "~zero"
590  ret i1 %0
591}
592
593define i1 @issubnormal_or_zero_d(double %x) {
594; CHECK32-LABEL: issubnormal_or_zero_d:
595; CHECK32:       # %bb.0: # %entry
596; CHECK32-NEXT:    fclass.d $fa0, $fa0
597; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
598; CHECK32-NEXT:    andi $a0, $a0, 816
599; CHECK32-NEXT:    sltu $a0, $zero, $a0
600; CHECK32-NEXT:    ret
601;
602; CHECK64-LABEL: issubnormal_or_zero_d:
603; CHECK64:       # %bb.0: # %entry
604; CHECK64-NEXT:    fclass.d $fa0, $fa0
605; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
606; CHECK64-NEXT:    andi $a0, $a0, 816
607; CHECK64-NEXT:    sltu $a0, $zero, $a0
608; CHECK64-NEXT:    ret
609entry:
610  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 240)  ; 0xf0 = "subnormal|zero"
611  ret i1 %0
612}
613
614define i1 @not_issubnormal_or_zero_d(double %x) {
615; CHECK32-LABEL: not_issubnormal_or_zero_d:
616; CHECK32:       # %bb.0: # %entry
617; CHECK32-NEXT:    fclass.d $fa0, $fa0
618; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
619; CHECK32-NEXT:    andi $a0, $a0, 207
620; CHECK32-NEXT:    sltu $a0, $zero, $a0
621; CHECK32-NEXT:    ret
622;
623; CHECK64-LABEL: not_issubnormal_or_zero_d:
624; CHECK64:       # %bb.0: # %entry
625; CHECK64-NEXT:    fclass.d $fa0, $fa0
626; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
627; CHECK64-NEXT:    andi $a0, $a0, 207
628; CHECK64-NEXT:    sltu $a0, $zero, $a0
629; CHECK64-NEXT:    ret
630entry:
631  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 783)  ; ~0xf0 = "~(subnormal|zero)"
632  ret i1 %0
633}
634
635define i1 @is_plus_zero_d(double %x) {
636; CHECK32-LABEL: is_plus_zero_d:
637; CHECK32:       # %bb.0: # %entry
638; CHECK32-NEXT:    fclass.d $fa0, $fa0
639; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
640; CHECK32-NEXT:    andi $a0, $a0, 512
641; CHECK32-NEXT:    sltu $a0, $zero, $a0
642; CHECK32-NEXT:    ret
643;
644; CHECK64-LABEL: is_plus_zero_d:
645; CHECK64:       # %bb.0: # %entry
646; CHECK64-NEXT:    fclass.d $fa0, $fa0
647; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
648; CHECK64-NEXT:    andi $a0, $a0, 512
649; CHECK64-NEXT:    sltu $a0, $zero, $a0
650; CHECK64-NEXT:    ret
651entry:
652  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 64)  ; 0x40 = "+zero"
653  ret i1 %0
654}
655
656define i1 @not_is_plus_zero_d(double %x) {
657; CHECK32-LABEL: not_is_plus_zero_d:
658; CHECK32:       # %bb.0: # %entry
659; CHECK32-NEXT:    fclass.d $fa0, $fa0
660; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
661; CHECK32-NEXT:    andi $a0, $a0, 511
662; CHECK32-NEXT:    sltu $a0, $zero, $a0
663; CHECK32-NEXT:    ret
664;
665; CHECK64-LABEL: not_is_plus_zero_d:
666; CHECK64:       # %bb.0: # %entry
667; CHECK64-NEXT:    fclass.d $fa0, $fa0
668; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
669; CHECK64-NEXT:    andi $a0, $a0, 511
670; CHECK64-NEXT:    sltu $a0, $zero, $a0
671; CHECK64-NEXT:    ret
672entry:
673  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 959)  ; ~0x40 = ~"+zero"
674  ret i1 %0
675}
676
677define i1 @is_minus_zero_d(double %x) {
678; CHECK32-LABEL: is_minus_zero_d:
679; CHECK32:       # %bb.0: # %entry
680; CHECK32-NEXT:    fclass.d $fa0, $fa0
681; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
682; CHECK32-NEXT:    andi $a0, $a0, 32
683; CHECK32-NEXT:    sltu $a0, $zero, $a0
684; CHECK32-NEXT:    ret
685;
686; CHECK64-LABEL: is_minus_zero_d:
687; CHECK64:       # %bb.0: # %entry
688; CHECK64-NEXT:    fclass.d $fa0, $fa0
689; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
690; CHECK64-NEXT:    andi $a0, $a0, 32
691; CHECK64-NEXT:    sltu $a0, $zero, $a0
692; CHECK64-NEXT:    ret
693entry:
694  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 32)  ; 0x20 = "-zero"
695  ret i1 %0
696}
697
698define i1 @not_is_minus_zero_d(double %x) {
699; CHECK32-LABEL: not_is_minus_zero_d:
700; CHECK32:       # %bb.0: # %entry
701; CHECK32-NEXT:    fclass.d $fa0, $fa0
702; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
703; CHECK32-NEXT:    andi $a0, $a0, 991
704; CHECK32-NEXT:    sltu $a0, $zero, $a0
705; CHECK32-NEXT:    ret
706;
707; CHECK64-LABEL: not_is_minus_zero_d:
708; CHECK64:       # %bb.0: # %entry
709; CHECK64-NEXT:    fclass.d $fa0, $fa0
710; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
711; CHECK64-NEXT:    andi $a0, $a0, 991
712; CHECK64-NEXT:    sltu $a0, $zero, $a0
713; CHECK64-NEXT:    ret
714entry:
715  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 991)  ; ~0x20 = ~"-zero"
716  ret i1 %0
717}
718
719define i1 @isnone_d(double %x) {
720; CHECK32-LABEL: isnone_d:
721; CHECK32:       # %bb.0: # %entry
722; CHECK32-NEXT:    fclass.d $fa0, $fa0
723; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
724; CHECK32-NEXT:    andi $a0, $a0, 0
725; CHECK32-NEXT:    sltu $a0, $zero, $a0
726; CHECK32-NEXT:    ret
727;
728; CHECK64-LABEL: isnone_d:
729; CHECK64:       # %bb.0: # %entry
730; CHECK64-NEXT:    fclass.d $fa0, $fa0
731; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
732; CHECK64-NEXT:    andi $a0, $a0, 0
733; CHECK64-NEXT:    sltu $a0, $zero, $a0
734; CHECK64-NEXT:    ret
735entry:
736  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 0)
737  ret i1 %0
738}
739
740define i1 @isany_d(double %x) {
741; CHECK32-LABEL: isany_d:
742; CHECK32:       # %bb.0: # %entry
743; CHECK32-NEXT:    fclass.d $fa0, $fa0
744; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
745; CHECK32-NEXT:    andi $a0, $a0, 1023
746; CHECK32-NEXT:    sltu $a0, $zero, $a0
747; CHECK32-NEXT:    ret
748;
749; CHECK64-LABEL: isany_d:
750; CHECK64:       # %bb.0: # %entry
751; CHECK64-NEXT:    fclass.d $fa0, $fa0
752; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
753; CHECK64-NEXT:    andi $a0, $a0, 1023
754; CHECK64-NEXT:    sltu $a0, $zero, $a0
755; CHECK64-NEXT:    ret
756entry:
757  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 1023)
758  ret i1 %0
759}
760
761define i1 @iszero_or_nan_d(double %x) {
762; CHECK32-LABEL: iszero_or_nan_d:
763; CHECK32:       # %bb.0: # %entry
764; CHECK32-NEXT:    fclass.d $fa0, $fa0
765; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
766; CHECK32-NEXT:    andi $a0, $a0, 547
767; CHECK32-NEXT:    sltu $a0, $zero, $a0
768; CHECK32-NEXT:    ret
769;
770; CHECK64-LABEL: iszero_or_nan_d:
771; CHECK64:       # %bb.0: # %entry
772; CHECK64-NEXT:    fclass.d $fa0, $fa0
773; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
774; CHECK64-NEXT:    andi $a0, $a0, 547
775; CHECK64-NEXT:    sltu $a0, $zero, $a0
776; CHECK64-NEXT:    ret
777entry:
778  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 99)  ; 0x60|0x3 = "zero|nan"
779  ret i1 %0
780}
781
782define i1 @not_iszero_or_nan_d(double %x) {
783; CHECK32-LABEL: not_iszero_or_nan_d:
784; CHECK32:       # %bb.0: # %entry
785; CHECK32-NEXT:    fclass.d $fa0, $fa0
786; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
787; CHECK32-NEXT:    andi $a0, $a0, 476
788; CHECK32-NEXT:    sltu $a0, $zero, $a0
789; CHECK32-NEXT:    ret
790;
791; CHECK64-LABEL: not_iszero_or_nan_d:
792; CHECK64:       # %bb.0: # %entry
793; CHECK64-NEXT:    fclass.d $fa0, $fa0
794; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
795; CHECK64-NEXT:    andi $a0, $a0, 476
796; CHECK64-NEXT:    sltu $a0, $zero, $a0
797; CHECK64-NEXT:    ret
798entry:
799  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 924)  ; ~0x60 = "~(zero|nan)"
800  ret i1 %0
801}
802
803define i1 @iszero_or_qnan_d(double %x) {
804; CHECK32-LABEL: iszero_or_qnan_d:
805; CHECK32:       # %bb.0: # %entry
806; CHECK32-NEXT:    fclass.d $fa0, $fa0
807; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
808; CHECK32-NEXT:    andi $a0, $a0, 546
809; CHECK32-NEXT:    sltu $a0, $zero, $a0
810; CHECK32-NEXT:    ret
811;
812; CHECK64-LABEL: iszero_or_qnan_d:
813; CHECK64:       # %bb.0: # %entry
814; CHECK64-NEXT:    fclass.d $fa0, $fa0
815; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
816; CHECK64-NEXT:    andi $a0, $a0, 546
817; CHECK64-NEXT:    sltu $a0, $zero, $a0
818; CHECK64-NEXT:    ret
819entry:
820  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 98)  ; 0x60|0x2 = "zero|qnan"
821  ret i1 %0
822}
823
824define i1 @iszero_or_snan_d(double %x) {
825; CHECK32-LABEL: iszero_or_snan_d:
826; CHECK32:       # %bb.0: # %entry
827; CHECK32-NEXT:    fclass.d $fa0, $fa0
828; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
829; CHECK32-NEXT:    andi $a0, $a0, 545
830; CHECK32-NEXT:    sltu $a0, $zero, $a0
831; CHECK32-NEXT:    ret
832;
833; CHECK64-LABEL: iszero_or_snan_d:
834; CHECK64:       # %bb.0: # %entry
835; CHECK64-NEXT:    fclass.d $fa0, $fa0
836; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
837; CHECK64-NEXT:    andi $a0, $a0, 545
838; CHECK64-NEXT:    sltu $a0, $zero, $a0
839; CHECK64-NEXT:    ret
840entry:
841  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 97)  ; 0x60|0x1 = "zero|snan"
842  ret i1 %0
843}
844
845define i1 @not_iszero_or_qnan_d(double %x) {
846; CHECK32-LABEL: not_iszero_or_qnan_d:
847; CHECK32:       # %bb.0: # %entry
848; CHECK32-NEXT:    fclass.d $fa0, $fa0
849; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
850; CHECK32-NEXT:    andi $a0, $a0, 477
851; CHECK32-NEXT:    sltu $a0, $zero, $a0
852; CHECK32-NEXT:    ret
853;
854; CHECK64-LABEL: not_iszero_or_qnan_d:
855; CHECK64:       # %bb.0: # %entry
856; CHECK64-NEXT:    fclass.d $fa0, $fa0
857; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
858; CHECK64-NEXT:    andi $a0, $a0, 477
859; CHECK64-NEXT:    sltu $a0, $zero, $a0
860; CHECK64-NEXT:    ret
861entry:
862  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 925)  ; ~(0x60|0x2) = "~(zero|qnan)"
863  ret i1 %0
864}
865
866define i1 @not_iszero_or_snan_d(double %x) {
867; CHECK32-LABEL: not_iszero_or_snan_d:
868; CHECK32:       # %bb.0: # %entry
869; CHECK32-NEXT:    fclass.d $fa0, $fa0
870; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
871; CHECK32-NEXT:    andi $a0, $a0, 478
872; CHECK32-NEXT:    sltu $a0, $zero, $a0
873; CHECK32-NEXT:    ret
874;
875; CHECK64-LABEL: not_iszero_or_snan_d:
876; CHECK64:       # %bb.0: # %entry
877; CHECK64-NEXT:    fclass.d $fa0, $fa0
878; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
879; CHECK64-NEXT:    andi $a0, $a0, 478
880; CHECK64-NEXT:    sltu $a0, $zero, $a0
881; CHECK64-NEXT:    ret
882entry:
883  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 926)  ; ~(0x60|0x1) = "~(zero|snan)"
884  ret i1 %0
885}
886
887define i1 @isinf_or_nan_d(double %x) {
888; CHECK32-LABEL: isinf_or_nan_d:
889; CHECK32:       # %bb.0: # %entry
890; CHECK32-NEXT:    fclass.d $fa0, $fa0
891; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
892; CHECK32-NEXT:    andi $a0, $a0, 71
893; CHECK32-NEXT:    sltu $a0, $zero, $a0
894; CHECK32-NEXT:    ret
895;
896; CHECK64-LABEL: isinf_or_nan_d:
897; CHECK64:       # %bb.0: # %entry
898; CHECK64-NEXT:    fclass.d $fa0, $fa0
899; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
900; CHECK64-NEXT:    andi $a0, $a0, 71
901; CHECK64-NEXT:    sltu $a0, $zero, $a0
902; CHECK64-NEXT:    ret
903entry:
904  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 519)  ; 0x204|0x3 = "inf|nan"
905  ret i1 %0
906}
907
908define i1 @not_isinf_or_nan_d(double %x) {
909; CHECK32-LABEL: not_isinf_or_nan_d:
910; CHECK32:       # %bb.0: # %entry
911; CHECK32-NEXT:    fclass.d $fa0, $fa0
912; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
913; CHECK32-NEXT:    andi $a0, $a0, 952
914; CHECK32-NEXT:    sltu $a0, $zero, $a0
915; CHECK32-NEXT:    ret
916;
917; CHECK64-LABEL: not_isinf_or_nan_d:
918; CHECK64:       # %bb.0: # %entry
919; CHECK64-NEXT:    fclass.d $fa0, $fa0
920; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
921; CHECK64-NEXT:    andi $a0, $a0, 952
922; CHECK64-NEXT:    sltu $a0, $zero, $a0
923; CHECK64-NEXT:    ret
924entry:
925  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 504)  ; ~(0x204|0x3) = "~(inf|nan)"
926  ret i1 %0
927}
928
929define i1 @isfinite_or_nan_d(double %x) {
930; CHECK32-LABEL: isfinite_or_nan_d:
931; CHECK32:       # %bb.0: # %entry
932; CHECK32-NEXT:    fclass.d $fa0, $fa0
933; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
934; CHECK32-NEXT:    andi $a0, $a0, 955
935; CHECK32-NEXT:    sltu $a0, $zero, $a0
936; CHECK32-NEXT:    ret
937;
938; CHECK64-LABEL: isfinite_or_nan_d:
939; CHECK64:       # %bb.0: # %entry
940; CHECK64-NEXT:    fclass.d $fa0, $fa0
941; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
942; CHECK64-NEXT:    andi $a0, $a0, 955
943; CHECK64-NEXT:    sltu $a0, $zero, $a0
944; CHECK64-NEXT:    ret
945entry:
946  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 507)  ; 0x1f8|0x3 = "finite|nan"
947  ret i1 %0
948}
949
950define i1 @not_isfinite_or_nan_d(double %x) {
951; CHECK32-LABEL: not_isfinite_or_nan_d:
952; CHECK32:       # %bb.0: # %entry
953; CHECK32-NEXT:    fclass.d $fa0, $fa0
954; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
955; CHECK32-NEXT:    andi $a0, $a0, 68
956; CHECK32-NEXT:    sltu $a0, $zero, $a0
957; CHECK32-NEXT:    ret
958;
959; CHECK64-LABEL: not_isfinite_or_nan_d:
960; CHECK64:       # %bb.0: # %entry
961; CHECK64-NEXT:    fclass.d $fa0, $fa0
962; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
963; CHECK64-NEXT:    andi $a0, $a0, 68
964; CHECK64-NEXT:    sltu $a0, $zero, $a0
965; CHECK64-NEXT:    ret
966entry:
967  %0 = tail call i1 @llvm.is.fpclass.f64(double %x, i32 516)  ; ~(0x1f8|0x3) = "~(finite|nan)"
968  ret i1 %0
969}
970
971define i1 @is_plus_inf_or_nan_d(double %x) {
972; CHECK32-LABEL: is_plus_inf_or_nan_d:
973; CHECK32:       # %bb.0:
974; CHECK32-NEXT:    fclass.d $fa0, $fa0
975; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
976; CHECK32-NEXT:    andi $a0, $a0, 67
977; CHECK32-NEXT:    sltu $a0, $zero, $a0
978; CHECK32-NEXT:    ret
979;
980; CHECK64-LABEL: is_plus_inf_or_nan_d:
981; CHECK64:       # %bb.0:
982; CHECK64-NEXT:    fclass.d $fa0, $fa0
983; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
984; CHECK64-NEXT:    andi $a0, $a0, 67
985; CHECK64-NEXT:    sltu $a0, $zero, $a0
986; CHECK64-NEXT:    ret
987  %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 515)  ; 0x200|0x3 = "+inf|nan"
988  ret i1 %class
989}
990
991define i1 @is_minus_inf_or_nan_d(double %x) {
992; CHECK32-LABEL: is_minus_inf_or_nan_d:
993; CHECK32:       # %bb.0:
994; CHECK32-NEXT:    fclass.d $fa0, $fa0
995; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
996; CHECK32-NEXT:    andi $a0, $a0, 7
997; CHECK32-NEXT:    sltu $a0, $zero, $a0
998; CHECK32-NEXT:    ret
999;
1000; CHECK64-LABEL: is_minus_inf_or_nan_d:
1001; CHECK64:       # %bb.0:
1002; CHECK64-NEXT:    fclass.d $fa0, $fa0
1003; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
1004; CHECK64-NEXT:    andi $a0, $a0, 7
1005; CHECK64-NEXT:    sltu $a0, $zero, $a0
1006; CHECK64-NEXT:    ret
1007  %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 7)  ; "-inf|nan"
1008  ret i1 %class
1009}
1010
1011define i1 @not_is_plus_inf_or_nan_d(double %x) {
1012; CHECK32-LABEL: not_is_plus_inf_or_nan_d:
1013; CHECK32:       # %bb.0:
1014; CHECK32-NEXT:    fclass.d $fa0, $fa0
1015; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
1016; CHECK32-NEXT:    andi $a0, $a0, 956
1017; CHECK32-NEXT:    sltu $a0, $zero, $a0
1018; CHECK32-NEXT:    ret
1019;
1020; CHECK64-LABEL: not_is_plus_inf_or_nan_d:
1021; CHECK64:       # %bb.0:
1022; CHECK64-NEXT:    fclass.d $fa0, $fa0
1023; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
1024; CHECK64-NEXT:    andi $a0, $a0, 956
1025; CHECK64-NEXT:    sltu $a0, $zero, $a0
1026; CHECK64-NEXT:    ret
1027  %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 508)  ; ~(0x200|0x3) = "~(+inf|nan)"
1028  ret i1 %class
1029}
1030
1031define i1 @not_is_minus_inf_or_nan_d(double %x) {
1032; CHECK32-LABEL: not_is_minus_inf_or_nan_d:
1033; CHECK32:       # %bb.0:
1034; CHECK32-NEXT:    fclass.d $fa0, $fa0
1035; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
1036; CHECK32-NEXT:    andi $a0, $a0, 1016
1037; CHECK32-NEXT:    sltu $a0, $zero, $a0
1038; CHECK32-NEXT:    ret
1039;
1040; CHECK64-LABEL: not_is_minus_inf_or_nan_d:
1041; CHECK64:       # %bb.0:
1042; CHECK64-NEXT:    fclass.d $fa0, $fa0
1043; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
1044; CHECK64-NEXT:    andi $a0, $a0, 1016
1045; CHECK64-NEXT:    sltu $a0, $zero, $a0
1046; CHECK64-NEXT:    ret
1047  %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 1016)  ; "~(-inf|nan)"
1048  ret i1 %class
1049}
1050
1051define i1 @is_plus_inf_or_snan_d(double %x) {
1052; CHECK32-LABEL: is_plus_inf_or_snan_d:
1053; CHECK32:       # %bb.0:
1054; CHECK32-NEXT:    fclass.d $fa0, $fa0
1055; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
1056; CHECK32-NEXT:    andi $a0, $a0, 65
1057; CHECK32-NEXT:    sltu $a0, $zero, $a0
1058; CHECK32-NEXT:    ret
1059;
1060; CHECK64-LABEL: is_plus_inf_or_snan_d:
1061; CHECK64:       # %bb.0:
1062; CHECK64-NEXT:    fclass.d $fa0, $fa0
1063; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
1064; CHECK64-NEXT:    andi $a0, $a0, 65
1065; CHECK64-NEXT:    sltu $a0, $zero, $a0
1066; CHECK64-NEXT:    ret
1067  %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 513)  ; 0x200|0x1 = "+inf|snan"
1068  ret i1 %class
1069}
1070
1071define i1 @is_plus_inf_or_qnan_d(double %x) {
1072; CHECK32-LABEL: is_plus_inf_or_qnan_d:
1073; CHECK32:       # %bb.0:
1074; CHECK32-NEXT:    fclass.d $fa0, $fa0
1075; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
1076; CHECK32-NEXT:    andi $a0, $a0, 66
1077; CHECK32-NEXT:    sltu $a0, $zero, $a0
1078; CHECK32-NEXT:    ret
1079;
1080; CHECK64-LABEL: is_plus_inf_or_qnan_d:
1081; CHECK64:       # %bb.0:
1082; CHECK64-NEXT:    fclass.d $fa0, $fa0
1083; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
1084; CHECK64-NEXT:    andi $a0, $a0, 66
1085; CHECK64-NEXT:    sltu $a0, $zero, $a0
1086; CHECK64-NEXT:    ret
1087  %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 514)  ; 0x200|0x1 = "+inf|qnan"
1088  ret i1 %class
1089}
1090
1091define i1 @not_is_plus_inf_or_snan_d(double %x) {
1092; CHECK32-LABEL: not_is_plus_inf_or_snan_d:
1093; CHECK32:       # %bb.0:
1094; CHECK32-NEXT:    fclass.d $fa0, $fa0
1095; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
1096; CHECK32-NEXT:    andi $a0, $a0, 958
1097; CHECK32-NEXT:    sltu $a0, $zero, $a0
1098; CHECK32-NEXT:    ret
1099;
1100; CHECK64-LABEL: not_is_plus_inf_or_snan_d:
1101; CHECK64:       # %bb.0:
1102; CHECK64-NEXT:    fclass.d $fa0, $fa0
1103; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
1104; CHECK64-NEXT:    andi $a0, $a0, 958
1105; CHECK64-NEXT:    sltu $a0, $zero, $a0
1106; CHECK64-NEXT:    ret
1107  %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 510) ; ~(+inf|snan)
1108  ret i1 %class
1109}
1110
1111define i1 @not_is_plus_inf_or_qnan_d(double %x) {
1112; CHECK32-LABEL: not_is_plus_inf_or_qnan_d:
1113; CHECK32:       # %bb.0:
1114; CHECK32-NEXT:    fclass.d $fa0, $fa0
1115; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
1116; CHECK32-NEXT:    andi $a0, $a0, 957
1117; CHECK32-NEXT:    sltu $a0, $zero, $a0
1118; CHECK32-NEXT:    ret
1119;
1120; CHECK64-LABEL: not_is_plus_inf_or_qnan_d:
1121; CHECK64:       # %bb.0:
1122; CHECK64-NEXT:    fclass.d $fa0, $fa0
1123; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
1124; CHECK64-NEXT:    andi $a0, $a0, 957
1125; CHECK64-NEXT:    sltu $a0, $zero, $a0
1126; CHECK64-NEXT:    ret
1127  %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 509) ; ~(+inf|qnan)
1128  ret i1 %class
1129}
1130
1131define i1 @is_minus_inf_or_snan_d(double %x) {
1132; CHECK32-LABEL: is_minus_inf_or_snan_d:
1133; CHECK32:       # %bb.0:
1134; CHECK32-NEXT:    fclass.d $fa0, $fa0
1135; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
1136; CHECK32-NEXT:    andi $a0, $a0, 5
1137; CHECK32-NEXT:    sltu $a0, $zero, $a0
1138; CHECK32-NEXT:    ret
1139;
1140; CHECK64-LABEL: is_minus_inf_or_snan_d:
1141; CHECK64:       # %bb.0:
1142; CHECK64-NEXT:    fclass.d $fa0, $fa0
1143; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
1144; CHECK64-NEXT:    andi $a0, $a0, 5
1145; CHECK64-NEXT:    sltu $a0, $zero, $a0
1146; CHECK64-NEXT:    ret
1147  %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 5)  ; "-inf|snan"
1148  ret i1 %class
1149}
1150
1151define i1 @is_minus_inf_or_qnan_d(double %x) {
1152; CHECK32-LABEL: is_minus_inf_or_qnan_d:
1153; CHECK32:       # %bb.0:
1154; CHECK32-NEXT:    fclass.d $fa0, $fa0
1155; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
1156; CHECK32-NEXT:    andi $a0, $a0, 6
1157; CHECK32-NEXT:    sltu $a0, $zero, $a0
1158; CHECK32-NEXT:    ret
1159;
1160; CHECK64-LABEL: is_minus_inf_or_qnan_d:
1161; CHECK64:       # %bb.0:
1162; CHECK64-NEXT:    fclass.d $fa0, $fa0
1163; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
1164; CHECK64-NEXT:    andi $a0, $a0, 6
1165; CHECK64-NEXT:    sltu $a0, $zero, $a0
1166; CHECK64-NEXT:    ret
1167  %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 6)  ; "-inf|qnan"
1168  ret i1 %class
1169}
1170
1171define i1 @not_is_minus_inf_or_snan_d(double %x) {
1172; CHECK32-LABEL: not_is_minus_inf_or_snan_d:
1173; CHECK32:       # %bb.0:
1174; CHECK32-NEXT:    fclass.d $fa0, $fa0
1175; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
1176; CHECK32-NEXT:    andi $a0, $a0, 1018
1177; CHECK32-NEXT:    sltu $a0, $zero, $a0
1178; CHECK32-NEXT:    ret
1179;
1180; CHECK64-LABEL: not_is_minus_inf_or_snan_d:
1181; CHECK64:       # %bb.0:
1182; CHECK64-NEXT:    fclass.d $fa0, $fa0
1183; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
1184; CHECK64-NEXT:    andi $a0, $a0, 1018
1185; CHECK64-NEXT:    sltu $a0, $zero, $a0
1186; CHECK64-NEXT:    ret
1187  %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 1018)  ; "~(-inf|snan)"
1188  ret i1 %class
1189}
1190
1191define i1 @not_is_minus_inf_or_qnan_d(double %x) {
1192; CHECK32-LABEL: not_is_minus_inf_or_qnan_d:
1193; CHECK32:       # %bb.0:
1194; CHECK32-NEXT:    fclass.d $fa0, $fa0
1195; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
1196; CHECK32-NEXT:    andi $a0, $a0, 1017
1197; CHECK32-NEXT:    sltu $a0, $zero, $a0
1198; CHECK32-NEXT:    ret
1199;
1200; CHECK64-LABEL: not_is_minus_inf_or_qnan_d:
1201; CHECK64:       # %bb.0:
1202; CHECK64-NEXT:    fclass.d $fa0, $fa0
1203; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
1204; CHECK64-NEXT:    andi $a0, $a0, 1017
1205; CHECK64-NEXT:    sltu $a0, $zero, $a0
1206; CHECK64-NEXT:    ret
1207  %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 1017)  ; "-inf|qnan"
1208  ret i1 %class
1209}
1210
1211define i1 @issubnormal_or_nan_d(double %x) {
1212; CHECK32-LABEL: issubnormal_or_nan_d:
1213; CHECK32:       # %bb.0:
1214; CHECK32-NEXT:    fclass.d $fa0, $fa0
1215; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
1216; CHECK32-NEXT:    andi $a0, $a0, 275
1217; CHECK32-NEXT:    sltu $a0, $zero, $a0
1218; CHECK32-NEXT:    ret
1219;
1220; CHECK64-LABEL: issubnormal_or_nan_d:
1221; CHECK64:       # %bb.0:
1222; CHECK64-NEXT:    fclass.d $fa0, $fa0
1223; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
1224; CHECK64-NEXT:    andi $a0, $a0, 275
1225; CHECK64-NEXT:    sltu $a0, $zero, $a0
1226; CHECK64-NEXT:    ret
1227  %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 147)  ; 0x90|0x3 = "subnormal|nan"
1228  ret i1 %class
1229}
1230
1231define i1 @issubnormal_or_zero_or_nan_d(double %x) {
1232; CHECK32-LABEL: issubnormal_or_zero_or_nan_d:
1233; CHECK32:       # %bb.0:
1234; CHECK32-NEXT:    fclass.d $fa0, $fa0
1235; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
1236; CHECK32-NEXT:    andi $a0, $a0, 819
1237; CHECK32-NEXT:    sltu $a0, $zero, $a0
1238; CHECK32-NEXT:    ret
1239;
1240; CHECK64-LABEL: issubnormal_or_zero_or_nan_d:
1241; CHECK64:       # %bb.0:
1242; CHECK64-NEXT:    fclass.d $fa0, $fa0
1243; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
1244; CHECK64-NEXT:    andi $a0, $a0, 819
1245; CHECK64-NEXT:    sltu $a0, $zero, $a0
1246; CHECK64-NEXT:    ret
1247  %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 243)  ; 0xf0|0x3 = "subnormal|zero|nan"
1248  ret i1 %class
1249}
1250
1251define i1 @issubnormal_or_zero_or_snan_d(double %x) {
1252; CHECK32-LABEL: issubnormal_or_zero_or_snan_d:
1253; CHECK32:       # %bb.0:
1254; CHECK32-NEXT:    fclass.d $fa0, $fa0
1255; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
1256; CHECK32-NEXT:    andi $a0, $a0, 817
1257; CHECK32-NEXT:    sltu $a0, $zero, $a0
1258; CHECK32-NEXT:    ret
1259;
1260; CHECK64-LABEL: issubnormal_or_zero_or_snan_d:
1261; CHECK64:       # %bb.0:
1262; CHECK64-NEXT:    fclass.d $fa0, $fa0
1263; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
1264; CHECK64-NEXT:    andi $a0, $a0, 817
1265; CHECK64-NEXT:    sltu $a0, $zero, $a0
1266; CHECK64-NEXT:    ret
1267  %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 241)  ; 0x90|0x1 = "subnormal|snan"
1268  ret i1 %class
1269}
1270
1271define i1 @issubnormal_or_zero_or_qnan_d(double %x) {
1272; CHECK32-LABEL: issubnormal_or_zero_or_qnan_d:
1273; CHECK32:       # %bb.0:
1274; CHECK32-NEXT:    fclass.d $fa0, $fa0
1275; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
1276; CHECK32-NEXT:    andi $a0, $a0, 818
1277; CHECK32-NEXT:    sltu $a0, $zero, $a0
1278; CHECK32-NEXT:    ret
1279;
1280; CHECK64-LABEL: issubnormal_or_zero_or_qnan_d:
1281; CHECK64:       # %bb.0:
1282; CHECK64-NEXT:    fclass.d $fa0, $fa0
1283; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
1284; CHECK64-NEXT:    andi $a0, $a0, 818
1285; CHECK64-NEXT:    sltu $a0, $zero, $a0
1286; CHECK64-NEXT:    ret
1287  %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 242)  ; 0x90|0x2 = "subnormal|qnan"
1288  ret i1 %class
1289}
1290
1291define i1 @not_issubnormal_or_nan_d(double %x) {
1292; CHECK32-LABEL: not_issubnormal_or_nan_d:
1293; CHECK32:       # %bb.0:
1294; CHECK32-NEXT:    fclass.d $fa0, $fa0
1295; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
1296; CHECK32-NEXT:    andi $a0, $a0, 748
1297; CHECK32-NEXT:    sltu $a0, $zero, $a0
1298; CHECK32-NEXT:    ret
1299;
1300; CHECK64-LABEL: not_issubnormal_or_nan_d:
1301; CHECK64:       # %bb.0:
1302; CHECK64-NEXT:    fclass.d $fa0, $fa0
1303; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
1304; CHECK64-NEXT:    andi $a0, $a0, 748
1305; CHECK64-NEXT:    sltu $a0, $zero, $a0
1306; CHECK64-NEXT:    ret
1307  %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 876)  ; ~(0x90|0x3) = ~"subnormal|nan"
1308  ret i1 %class
1309}
1310
1311define i1 @not_issubnormal_or_zero_or_nan_d(double %x) {
1312; CHECK32-LABEL: not_issubnormal_or_zero_or_nan_d:
1313; CHECK32:       # %bb.0:
1314; CHECK32-NEXT:    fclass.d $fa0, $fa0
1315; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
1316; CHECK32-NEXT:    andi $a0, $a0, 204
1317; CHECK32-NEXT:    sltu $a0, $zero, $a0
1318; CHECK32-NEXT:    ret
1319;
1320; CHECK64-LABEL: not_issubnormal_or_zero_or_nan_d:
1321; CHECK64:       # %bb.0:
1322; CHECK64-NEXT:    fclass.d $fa0, $fa0
1323; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
1324; CHECK64-NEXT:    andi $a0, $a0, 204
1325; CHECK64-NEXT:    sltu $a0, $zero, $a0
1326; CHECK64-NEXT:    ret
1327  %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 780)  ; ~(0xf0|0x3) = ~"subnormal|zero|nan"
1328  ret i1 %class
1329}
1330
1331define i1 @not_issubnormal_or_zero_or_snan_d(double %x) {
1332; CHECK32-LABEL: not_issubnormal_or_zero_or_snan_d:
1333; CHECK32:       # %bb.0:
1334; CHECK32-NEXT:    fclass.d $fa0, $fa0
1335; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
1336; CHECK32-NEXT:    andi $a0, $a0, 206
1337; CHECK32-NEXT:    sltu $a0, $zero, $a0
1338; CHECK32-NEXT:    ret
1339;
1340; CHECK64-LABEL: not_issubnormal_or_zero_or_snan_d:
1341; CHECK64:       # %bb.0:
1342; CHECK64-NEXT:    fclass.d $fa0, $fa0
1343; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
1344; CHECK64-NEXT:    andi $a0, $a0, 206
1345; CHECK64-NEXT:    sltu $a0, $zero, $a0
1346; CHECK64-NEXT:    ret
1347  %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 782)  ; ~(0x90|0x1) = ~"subnormal|snan"
1348  ret i1 %class
1349}
1350
1351define i1 @not_issubnormal_or_zero_or_qnan_d(double %x) {
1352; CHECK32-LABEL: not_issubnormal_or_zero_or_qnan_d:
1353; CHECK32:       # %bb.0:
1354; CHECK32-NEXT:    fclass.d $fa0, $fa0
1355; CHECK32-NEXT:    movfr2gr.s $a0, $fa0
1356; CHECK32-NEXT:    andi $a0, $a0, 205
1357; CHECK32-NEXT:    sltu $a0, $zero, $a0
1358; CHECK32-NEXT:    ret
1359;
1360; CHECK64-LABEL: not_issubnormal_or_zero_or_qnan_d:
1361; CHECK64:       # %bb.0:
1362; CHECK64-NEXT:    fclass.d $fa0, $fa0
1363; CHECK64-NEXT:    movfr2gr.d $a0, $fa0
1364; CHECK64-NEXT:    andi $a0, $a0, 205
1365; CHECK64-NEXT:    sltu $a0, $zero, $a0
1366; CHECK64-NEXT:    ret
1367  %class = tail call i1 @llvm.is.fpclass.f64(double %x, i32 781)  ; ~(0x90|0x2) = ~"subnormal|qnan"
1368  ret i1 %class
1369}
1370
1371declare i1 @llvm.is.fpclass.f64(double, i32)
1372