xref: /llvm-project/llvm/test/CodeGen/LoongArch/ir-instruction/sdiv-udiv-srem-urem-div32.ll (revision f6289f13088aa8898fe389f7bb80cca79ea64c8a) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc --mtriple=loongarch64 -mattr=+d,-div32 < %s | FileCheck %s --check-prefix=LA64
3; RUN: llc --mtriple=loongarch64 -mattr=+d,+div32 < %s | FileCheck %s --check-prefix=LA64-DIV32
4
5define i32 @divw(i64 %a, i64 %b) {
6; LA64-LABEL: divw:
7; LA64:       # %bb.0:
8; LA64-NEXT:    addi.w $a1, $a1, 0
9; LA64-NEXT:    addi.w $a0, $a0, 0
10; LA64-NEXT:    div.w $a0, $a0, $a1
11; LA64-NEXT:    ret
12;
13; LA64-DIV32-LABEL: divw:
14; LA64-DIV32:       # %bb.0:
15; LA64-DIV32-NEXT:    div.w $a0, $a0, $a1
16; LA64-DIV32-NEXT:    ret
17  %conv1 = trunc i64 %a to i32
18  %conv2 = trunc i64 %b to i32
19  %r = sdiv i32 %conv1, %conv2
20  ret i32 %r
21}
22
23define i32  @divwu(i64 %a, i64 %b) {
24; LA64-LABEL: divwu:
25; LA64:       # %bb.0:
26; LA64-NEXT:    addi.w $a1, $a1, 0
27; LA64-NEXT:    addi.w $a0, $a0, 0
28; LA64-NEXT:    div.wu $a0, $a0, $a1
29; LA64-NEXT:    ret
30;
31; LA64-DIV32-LABEL: divwu:
32; LA64-DIV32:       # %bb.0:
33; LA64-DIV32-NEXT:    div.wu $a0, $a0, $a1
34; LA64-DIV32-NEXT:    ret
35  %conv1 = trunc i64 %a to i32
36  %conv2 = trunc i64 %b to i32
37  %r = udiv i32 %conv1, %conv2
38  ret i32 %r
39}
40
41define i32 @modw(i64 %a, i64 %b) {
42; LA64-LABEL: modw:
43; LA64:       # %bb.0:
44; LA64-NEXT:    addi.w $a1, $a1, 0
45; LA64-NEXT:    addi.w $a0, $a0, 0
46; LA64-NEXT:    mod.w $a0, $a0, $a1
47; LA64-NEXT:    ret
48;
49; LA64-DIV32-LABEL: modw:
50; LA64-DIV32:       # %bb.0:
51; LA64-DIV32-NEXT:    mod.w $a0, $a0, $a1
52; LA64-DIV32-NEXT:    ret
53  %conv1 = trunc i64 %a to i32
54  %conv2 = trunc i64 %b to i32
55  %r = srem i32 %conv1, %conv2
56  ret i32 %r
57}
58
59define i32 @modwu(i64 %a, i64 %b) {
60; LA64-LABEL: modwu:
61; LA64:       # %bb.0:
62; LA64-NEXT:    addi.w $a1, $a1, 0
63; LA64-NEXT:    addi.w $a0, $a0, 0
64; LA64-NEXT:    mod.wu $a0, $a0, $a1
65; LA64-NEXT:    ret
66;
67; LA64-DIV32-LABEL: modwu:
68; LA64-DIV32:       # %bb.0:
69; LA64-DIV32-NEXT:    mod.wu $a0, $a0, $a1
70; LA64-DIV32-NEXT:    ret
71  %conv1 = trunc i64 %a to i32
72  %conv2 = trunc i64 %b to i32
73  %r = urem i32 %conv1, %conv2
74  ret i32 %r
75}
76
77define signext i32 @sextw_rmv(i32 signext %a, i32 signext %b, i32 signext %c) {
78; LA64-LABEL: sextw_rmv:
79; LA64:       # %bb.0: # %entry
80; LA64-NEXT:    mul.w $a0, $a1, $a0
81; LA64-NEXT:    div.w $a1, $a2, $a0
82; LA64-NEXT:    sltu $a0, $a1, $a0
83; LA64-NEXT:    ret
84;
85; LA64-DIV32-LABEL: sextw_rmv:
86; LA64-DIV32:       # %bb.0: # %entry
87; LA64-DIV32-NEXT:    mul.w $a0, $a1, $a0
88; LA64-DIV32-NEXT:    div.w $a1, $a2, $a0
89; LA64-DIV32-NEXT:    sltu $a0, $a1, $a0
90; LA64-DIV32-NEXT:    ret
91entry:
92  %mul = mul nsw i32 %b, %a
93  %div = sdiv i32 %c, %mul
94  %cmp = icmp ult i32 %div, %mul
95  %conv = zext i1 %cmp to i32
96  ret i32 %conv
97}
98