1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc --mtriple=loongarch32 -mattr=+d --verify-machineinstrs < %s \ 3; RUN: | FileCheck --check-prefix=LA32 %s 4; RUN: llc --mtriple=loongarch64 -mattr=+d --verify-machineinstrs < %s \ 5; RUN: | FileCheck --check-prefix=LA64 %s 6 7;; These test that we can use architectural names ($r*) refer to registers in 8;; inline asm constraint lists. In each case, the named register should be used 9;; for the source register of the `addi.w`. It is very likely that `$a0` will 10;; be chosen as the designation register, but this is left to the compiler to 11;; choose. 12;; 13;; Parenthesised registers in comments are the other aliases for this register. 14 15;; NOTE: This test has to pass in 0 to the inline asm, because that's the only 16;; value `$r0` (`$zero`) can take. 17define i32 @register_r0() nounwind { 18; LA32-LABEL: register_r0: 19; LA32: # %bb.0: 20; LA32-NEXT: #APP 21; LA32-NEXT: addi.w $a0, $zero, 0 22; LA32-NEXT: #NO_APP 23; LA32-NEXT: ret 24; 25; LA64-LABEL: register_r0: 26; LA64: # %bb.0: 27; LA64-NEXT: #APP 28; LA64-NEXT: addi.w $a0, $zero, 0 29; LA64-NEXT: #NO_APP 30; LA64-NEXT: ret 31 %1 = tail call i32 asm "addi.w $0, $1, 0", "=r,{$r0}"(i32 0) 32 ret i32 %1 33} 34 35define i32 @register_r4(i32 %a) nounwind { 36; LA32-LABEL: register_r4: 37; LA32: # %bb.0: 38; LA32-NEXT: #APP 39; LA32-NEXT: addi.w $a0, $a0, 1 40; LA32-NEXT: #NO_APP 41; LA32-NEXT: ret 42; 43; LA64-LABEL: register_r4: 44; LA64: # %bb.0: 45; LA64-NEXT: #APP 46; LA64-NEXT: addi.w $a0, $a0, 1 47; LA64-NEXT: #NO_APP 48; LA64-NEXT: ret 49 %1 = tail call i32 asm "addi.w $0, $1, 1", "=r,{$r4}"(i32 %a) 50 ret i32 %1 51} 52 53;; NOTE: This test uses `$r22` (`$s9`, `$fp`) as an input, so it should be saved. 54define i32 @register_r22(i32 %a) nounwind { 55; LA32-LABEL: register_r22: 56; LA32: # %bb.0: 57; LA32-NEXT: addi.w $sp, $sp, -16 58; LA32-NEXT: st.w $fp, $sp, 12 # 4-byte Folded Spill 59; LA32-NEXT: move $fp, $a0 60; LA32-NEXT: #APP 61; LA32-NEXT: addi.w $a0, $fp, 1 62; LA32-NEXT: #NO_APP 63; LA32-NEXT: ld.w $fp, $sp, 12 # 4-byte Folded Reload 64; LA32-NEXT: addi.w $sp, $sp, 16 65; LA32-NEXT: ret 66; 67; LA64-LABEL: register_r22: 68; LA64: # %bb.0: 69; LA64-NEXT: addi.d $sp, $sp, -16 70; LA64-NEXT: st.d $fp, $sp, 8 # 8-byte Folded Spill 71; LA64-NEXT: move $fp, $a0 72; LA64-NEXT: #APP 73; LA64-NEXT: addi.w $a0, $fp, 1 74; LA64-NEXT: #NO_APP 75; LA64-NEXT: ld.d $fp, $sp, 8 # 8-byte Folded Reload 76; LA64-NEXT: addi.d $sp, $sp, 16 77; LA64-NEXT: ret 78 %1 = tail call i32 asm "addi.w $0, $1, 1", "=r,{$r22}"(i32 %a) 79 ret i32 %1 80} 81 82;; NOTE: This test uses `$r31` (`$s8`) as an input, so it should be saved. 83define i32 @register_r31(i32 %a) nounwind { 84; LA32-LABEL: register_r31: 85; LA32: # %bb.0: 86; LA32-NEXT: addi.w $sp, $sp, -16 87; LA32-NEXT: st.w $s8, $sp, 12 # 4-byte Folded Spill 88; LA32-NEXT: move $s8, $a0 89; LA32-NEXT: #APP 90; LA32-NEXT: addi.w $a0, $s8, 1 91; LA32-NEXT: #NO_APP 92; LA32-NEXT: ld.w $s8, $sp, 12 # 4-byte Folded Reload 93; LA32-NEXT: addi.w $sp, $sp, 16 94; LA32-NEXT: ret 95; 96; LA64-LABEL: register_r31: 97; LA64: # %bb.0: 98; LA64-NEXT: addi.d $sp, $sp, -16 99; LA64-NEXT: st.d $s8, $sp, 8 # 8-byte Folded Spill 100; LA64-NEXT: move $s8, $a0 101; LA64-NEXT: #APP 102; LA64-NEXT: addi.w $a0, $s8, 1 103; LA64-NEXT: #NO_APP 104; LA64-NEXT: ld.d $s8, $sp, 8 # 8-byte Folded Reload 105; LA64-NEXT: addi.d $sp, $sp, 16 106; LA64-NEXT: ret 107 %1 = tail call i32 asm "addi.w $0, $1, 1", "=r,{$r31}"(i32 %a) 108 ret i32 %1 109} 110