1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc --mtriple=loongarch32 --mattr=+f,+d --target-abi=ilp32d --verify-machineinstrs < %s \ 3; RUN: | FileCheck --check-prefix=LA32 %s 4; RUN: llc --mtriple=loongarch64 --mattr=+f,+d --target-abi=lp64d --verify-machineinstrs < %s \ 5; RUN: | FileCheck --check-prefix=LA64 %s 6 7;; These test that we can use architectural names ($f[0-9]*) refer to registers in 8;; inline asm constraint lists. In each case, the named register should be used 9;; for the source register of the `fabs.d`. It is very likely that `$fa0` will 10;; be chosen as the designation register, but this is left to the compiler to 11;; choose. 12;; 13;; Parenthesised registers in comments are the other aliases for this register. 14 15define double @register_f0(double %a) nounwind { 16; LA32-LABEL: register_f0: 17; LA32: # %bb.0: 18; LA32-NEXT: #APP 19; LA32-NEXT: fabs.d $fa0, $fa0 20; LA32-NEXT: #NO_APP 21; LA32-NEXT: ret 22; 23; LA64-LABEL: register_f0: 24; LA64: # %bb.0: 25; LA64-NEXT: #APP 26; LA64-NEXT: fabs.d $fa0, $fa0 27; LA64-NEXT: #NO_APP 28; LA64-NEXT: ret 29 %1 = tail call double asm "fabs.d $0, $1", "=f,{$f0}"(double %a) 30 ret double %1 31} 32 33;; NOTE: This test uses `$f24` (`$fs0`) as an input, so it should be saved. 34define double @register_f24(double %a) nounwind { 35; LA32-LABEL: register_f24: 36; LA32: # %bb.0: 37; LA32-NEXT: addi.w $sp, $sp, -16 38; LA32-NEXT: fst.d $fs0, $sp, 8 # 8-byte Folded Spill 39; LA32-NEXT: fmov.d $fs0, $fa0 40; LA32-NEXT: #APP 41; LA32-NEXT: fabs.d $fa0, $fs0 42; LA32-NEXT: #NO_APP 43; LA32-NEXT: fld.d $fs0, $sp, 8 # 8-byte Folded Reload 44; LA32-NEXT: addi.w $sp, $sp, 16 45; LA32-NEXT: ret 46; 47; LA64-LABEL: register_f24: 48; LA64: # %bb.0: 49; LA64-NEXT: addi.d $sp, $sp, -16 50; LA64-NEXT: fst.d $fs0, $sp, 8 # 8-byte Folded Spill 51; LA64-NEXT: fmov.d $fs0, $fa0 52; LA64-NEXT: #APP 53; LA64-NEXT: fabs.d $fa0, $fs0 54; LA64-NEXT: #NO_APP 55; LA64-NEXT: fld.d $fs0, $sp, 8 # 8-byte Folded Reload 56; LA64-NEXT: addi.d $sp, $sp, 16 57; LA64-NEXT: ret 58 %1 = tail call double asm "fabs.d $0, $1", "=f,{$f24}"(double %a) 59 ret double %1 60} 61 62;; NOTE: This test uses `$f31` (`$fs7`) as an input, so it should be saved. 63define double @register_f31(double %a) nounwind { 64; LA32-LABEL: register_f31: 65; LA32: # %bb.0: 66; LA32-NEXT: addi.w $sp, $sp, -16 67; LA32-NEXT: fst.d $fs7, $sp, 8 # 8-byte Folded Spill 68; LA32-NEXT: fmov.d $fs7, $fa0 69; LA32-NEXT: #APP 70; LA32-NEXT: fabs.d $fa0, $fs7 71; LA32-NEXT: #NO_APP 72; LA32-NEXT: fld.d $fs7, $sp, 8 # 8-byte Folded Reload 73; LA32-NEXT: addi.w $sp, $sp, 16 74; LA32-NEXT: ret 75; 76; LA64-LABEL: register_f31: 77; LA64: # %bb.0: 78; LA64-NEXT: addi.d $sp, $sp, -16 79; LA64-NEXT: fst.d $fs7, $sp, 8 # 8-byte Folded Spill 80; LA64-NEXT: fmov.d $fs7, $fa0 81; LA64-NEXT: #APP 82; LA64-NEXT: fabs.d $fa0, $fs7 83; LA64-NEXT: #NO_APP 84; LA64-NEXT: fld.d $fs7, $sp, 8 # 8-byte Folded Reload 85; LA64-NEXT: addi.d $sp, $sp, 16 86; LA64-NEXT: ret 87 %1 = tail call double asm "fabs.d $0, $1", "=f,{$f31}"(double %a) 88 ret double %1 89} 90