xref: /llvm-project/llvm/test/CodeGen/LoongArch/imm.ll (revision eaf87d32754beb5bec10bab517bf56e25575b48e) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc --mtriple=loongarch64 -mattr=+d < %s | FileCheck %s
3
4define i64 @imm0() {
5; CHECK-LABEL: imm0:
6; CHECK:       # %bb.0:
7; CHECK-NEXT:    move $a0, $zero
8; CHECK-NEXT:    ret
9  ret i64 0
10}
11
12define i64 @imm7ff0000000000000() {
13; CHECK-LABEL: imm7ff0000000000000:
14; CHECK:       # %bb.0:
15; CHECK-NEXT:    lu52i.d $a0, $zero, 2047
16; CHECK-NEXT:    ret
17  ret i64 9218868437227405312
18}
19
20define i64 @imm0000000000000fff() {
21; CHECK-LABEL: imm0000000000000fff:
22; CHECK:       # %bb.0:
23; CHECK-NEXT:    ori $a0, $zero, 4095
24; CHECK-NEXT:    ret
25  ret i64 4095
26}
27
28define i64 @imm0007ffff00000800() {
29; CHECK-LABEL: imm0007ffff00000800:
30; CHECK:       # %bb.0:
31; CHECK-NEXT:    ori $a0, $zero, 2048
32; CHECK-NEXT:    lu32i.d $a0, 524287
33; CHECK-NEXT:    ret
34  ret i64 2251795518720000
35}
36
37define i64 @immfff0000000000fff() {
38; CHECK-LABEL: immfff0000000000fff:
39; CHECK:       # %bb.0:
40; CHECK-NEXT:    ori $a0, $zero, 4095
41; CHECK-NEXT:    lu52i.d $a0, $a0, -1
42; CHECK-NEXT:    ret
43  ret i64 -4503599627366401
44}
45
46define i64 @imm0008000000000fff() {
47; CHECK-LABEL: imm0008000000000fff:
48; CHECK:       # %bb.0:
49; CHECK-NEXT:    ori $a0, $zero, 4095
50; CHECK-NEXT:    bstrins.d $a0, $a0, 51, 51
51; CHECK-NEXT:    ret
52  ret i64 2251799813689343
53}
54
55define i64 @immfffffffffffff800() {
56; CHECK-LABEL: immfffffffffffff800:
57; CHECK:       # %bb.0:
58; CHECK-NEXT:    addi.w $a0, $zero, -2048
59; CHECK-NEXT:    ret
60  ret i64 -2048
61}
62
63define i64 @imm00000000fffff800() {
64; CHECK-LABEL: imm00000000fffff800:
65; CHECK:       # %bb.0:
66; CHECK-NEXT:    addi.w $a0, $zero, -2048
67; CHECK-NEXT:    lu32i.d $a0, 0
68; CHECK-NEXT:    ret
69  ret i64 4294965248
70}
71
72define i64 @imm000ffffffffff800() {
73; CHECK-LABEL: imm000ffffffffff800:
74; CHECK:       # %bb.0:
75; CHECK-NEXT:    addi.w $a0, $zero, -2048
76; CHECK-NEXT:    lu52i.d $a0, $a0, 0
77; CHECK-NEXT:    ret
78  ret i64 4503599627368448
79}
80
81define i64 @imm00080000fffff800() {
82; CHECK-LABEL: imm00080000fffff800:
83; CHECK:       # %bb.0:
84; CHECK-NEXT:    addi.w $a0, $zero, -2048
85; CHECK-NEXT:    lu32i.d $a0, -524288
86; CHECK-NEXT:    lu52i.d $a0, $a0, 0
87; CHECK-NEXT:    ret
88  ret i64 2251804108650496
89}
90
91define i64 @imm000000007ffff000() {
92; CHECK-LABEL: imm000000007ffff000:
93; CHECK:       # %bb.0:
94; CHECK-NEXT:    lu12i.w $a0, 524287
95; CHECK-NEXT:    ret
96  ret i64 2147479552
97}
98
99define i64 @imm0000000080000000() {
100; CHECK-LABEL: imm0000000080000000:
101; CHECK:       # %bb.0:
102; CHECK-NEXT:    lu12i.w $a0, -524288
103; CHECK-NEXT:    lu32i.d $a0, 0
104; CHECK-NEXT:    ret
105  ret i64 2147483648
106}
107
108define i64 @imm000ffffffffff000() {
109; CHECK-LABEL: imm000ffffffffff000:
110; CHECK:       # %bb.0:
111; CHECK-NEXT:    lu12i.w $a0, -1
112; CHECK-NEXT:    lu52i.d $a0, $a0, 0
113; CHECK-NEXT:    ret
114  ret i64 4503599627366400
115}
116
117define i64 @imm7ff0000080000000() {
118; CHECK-LABEL: imm7ff0000080000000:
119; CHECK:       # %bb.0:
120; CHECK-NEXT:    lu12i.w $a0, -524288
121; CHECK-NEXT:    lu32i.d $a0, 0
122; CHECK-NEXT:    lu52i.d $a0, $a0, 2047
123; CHECK-NEXT:    ret
124  ret i64 9218868439374888960
125}
126
127define i64 @immffffffff80000800() {
128; CHECK-LABEL: immffffffff80000800:
129; CHECK:       # %bb.0:
130; CHECK-NEXT:    lu12i.w $a0, -524288
131; CHECK-NEXT:    ori $a0, $a0, 2048
132; CHECK-NEXT:    ret
133  ret i64 -2147481600
134}
135
136define i64 @immffffffff7ffff800() {
137; CHECK-LABEL: immffffffff7ffff800:
138; CHECK:       # %bb.0:
139; CHECK-NEXT:    lu12i.w $a0, 524287
140; CHECK-NEXT:    ori $a0, $a0, 2048
141; CHECK-NEXT:    lu32i.d $a0, -1
142; CHECK-NEXT:    ret
143  ret i64 -2147485696
144}
145
146define i64 @imm7fffffff800007ff() {
147; CHECK-LABEL: imm7fffffff800007ff:
148; CHECK:       # %bb.0:
149; CHECK-NEXT:    lu12i.w $a0, -524288
150; CHECK-NEXT:    ori $a0, $a0, 2047
151; CHECK-NEXT:    lu52i.d $a0, $a0, 2047
152; CHECK-NEXT:    ret
153  ret i64 9223372034707294207
154}
155
156define i64 @imm0008000080000800() {
157; CHECK-LABEL: imm0008000080000800:
158; CHECK:       # %bb.0:
159; CHECK-NEXT:    lu12i.w $a0, -524288
160; CHECK-NEXT:    ori $a0, $a0, 2048
161; CHECK-NEXT:    lu32i.d $a0, -524288
162; CHECK-NEXT:    lu52i.d $a0, $a0, 0
163; CHECK-NEXT:    ret
164  ret i64 2251801961170944
165}
166
167define i64 @imm14000000a() {
168; CHECK-LABEL: imm14000000a:
169; CHECK:       # %bb.0:
170; CHECK-NEXT:    ori $a0, $zero, 10
171; CHECK-NEXT:    bstrins.d $a0, $a0, 32, 29
172; CHECK-NEXT:    ret
173  ret i64 5368709130
174}
175
176define i64 @imm0fff000000000fff() {
177; CHECK-LABEL: imm0fff000000000fff:
178; CHECK:       # %bb.0:
179; CHECK-NEXT:    ori $a0, $zero, 4095
180; CHECK-NEXT:    bstrins.d $a0, $a0, 59, 48
181; CHECK-NEXT:    ret
182  ret i64 1152640029630140415
183}
184
185define i64 @immffecffffffffffec() {
186; CHECK-LABEL: immffecffffffffffec:
187; CHECK:       # %bb.0:
188; CHECK-NEXT:    addi.w $a0, $zero, -20
189; CHECK-NEXT:    bstrins.d $a0, $a0, 52, 48
190; CHECK-NEXT:    ret
191  ret i64 -5348024557502484
192}
193
194define i64 @imm1c000000700000() {
195; CHECK-LABEL: imm1c000000700000:
196; CHECK:       # %bb.0:
197; CHECK-NEXT:    lu12i.w $a0, 1792
198; CHECK-NEXT:    bstrins.d $a0, $a0, 52, 30
199; CHECK-NEXT:    ret
200  ret i64 7881299355238400
201}
202
203define i64 @immf0f0f0f0f0f0f0f0() {
204; CHECK-LABEL: immf0f0f0f0f0f0f0f0:
205; CHECK:       # %bb.0:
206; CHECK-NEXT:    lu12i.w $a0, -61681
207; CHECK-NEXT:    ori $a0, $a0, 240
208; CHECK-NEXT:    bstrins.d $a0, $a0, 59, 32
209; CHECK-NEXT:    ret
210  ret i64 -1085102592571150096
211}
212
213define i64 @imm110000014000000a() {
214; CHECK-LABEL: imm110000014000000a:
215; CHECK:       # %bb.0:
216; CHECK-NEXT:    ori $a0, $zero, 10
217; CHECK-NEXT:    lu52i.d $a0, $a0, 272
218; CHECK-NEXT:    bstrins.d $a0, $a0, 32, 29
219; CHECK-NEXT:    ret
220  ret i64 1224979104013484042
221}
222