1; RUN: llc --mtriple=loongarch64 --relocation-model=pic \ 2; RUN: --code-model=medium < %s | FileCheck --check-prefix=MEDIUM %s 3; RUN: llc --mtriple=loongarch64 --relocation-model=pic \ 4; RUN: --code-model=large < %s | FileCheck --check-prefix=LARGE %s 5; RUN: llc --mtriple=loongarch64 --relocation-model=pic \ 6; RUN: --enable-tlsdesc --code-model=large < %s | \ 7; RUN: FileCheck --check-prefix=LARGEDESC %s 8 9; Check the adjancency of pseudo-instruction expansions to ensure 10; compliance with psABI requirements: 11; https://github.com/loongson/la-abi-specs/releases/tag/v2.30 12 13declare void @llvm.memset.p0.i64(ptr, i8, i64, i1) 14 15define void @call_external_sym(ptr %dst) { 16; LARGE-LABEL: call_external_sym: 17; LARGE: pcalau12i [[REG1:\$[a-z0-9]+]], %got_pc_hi20(memset) 18; LARGE-NEXT: addi.d [[REG2:\$[a-z0-9]+]], $zero, %got_pc_lo12(memset) 19; LARGE-NEXT: lu32i.d [[REG2]], %got64_pc_lo20(memset) 20; LARGE-NEXT: lu52i.d [[REG2]], [[REG2]], %got64_pc_hi12(memset) 21entry: 22 call void @llvm.memset.p0.i64(ptr %dst, i8 0, i64 1000, i1 false) 23 ret void 24} 25 26declare i32 @callee_tail(i32 %i) 27 28define i32 @caller_call_tail(i32 %i) nounwind { 29; MEDIUM-LABEL: caller_call_tail: 30; MEDIUM: pcaddu18i $t8, %call36(callee_tail) 31; MEDIUM-NEXT: jr $t8 32; 33; LARGE-LABEL: caller_call_tail: 34; LARGE: pcalau12i [[REG1:\$[a-z0-9]+]], %got_pc_hi20(callee_tail) 35; LARGE-NEXT: addi.d [[REG2:\$[a-z0-9]+]], $zero, %got_pc_lo12(callee_tail) 36; LARGE-NEXT: lu32i.d [[REG2]], %got64_pc_lo20(callee_tail) 37; LARGE-NEXT: lu52i.d [[REG2]], [[REG2]], %got64_pc_hi12(callee_tail) 38entry: 39 call i32 @callee_tail(i32 %i) 40 %r = tail call i32 @callee_tail(i32 %i) 41 ret i32 %r 42} 43 44@ie = external thread_local(initialexec) global i32 45 46define void @test_la_tls_ie(i32 signext %n) { 47; LARGE-LABEL: test_la_tls_ie: 48; LARGE: pcalau12i [[REG1:\$[a-z0-9]+]], %ie_pc_hi20(ie) 49; LARGE-NEXT: addi.d [[REG2:\$[a-z0-9]+]], $zero, %ie_pc_lo12(ie) 50; LARGE-NEXT: lu32i.d [[REG2]], %ie64_pc_lo20(ie) 51; LARGE-NEXT: lu52i.d [[REG2]], [[REG2]], %ie64_pc_hi12(ie) 52entry: 53 br label %loop 54 55loop: 56 %i = phi i32 [ %inc, %loop ], [ 0, %entry ] 57 %0 = load volatile i32, ptr @ie, align 4 58 %inc = add nuw nsw i32 %i, 1 59 %cmp = icmp slt i32 %inc, %n 60 br i1 %cmp, label %loop, label %ret 61 62ret: 63 ret void 64} 65 66@ld = external thread_local(localdynamic) global i32 67 68define void @test_la_tls_ld(i32 signext %n) { 69; LARGE-LABEL: test_la_tls_ld: 70; LARGE: pcalau12i [[REG1:\$[a-z0-9]+]], %ld_pc_hi20(ld) 71; LARGE-NEXT: addi.d [[REG2:\$[a-z0-9]+]], $zero, %got_pc_lo12(ld) 72; LARGE-NEXT: lu32i.d [[REG2]], %got64_pc_lo20(ld) 73; LARGE-NEXT: lu52i.d [[REG2]], [[REG2]], %got64_pc_hi12(ld) 74entry: 75 br label %loop 76 77loop: 78 %i = phi i32 [ %inc, %loop ], [ 0, %entry ] 79 %0 = load volatile i32, ptr @ld, align 4 80 %inc = add nuw nsw i32 %i, 1 81 %cmp = icmp slt i32 %inc, %n 82 br i1 %cmp, label %loop, label %ret 83 84ret: 85 ret void 86} 87 88@gd = external thread_local global i32 89 90define void @test_la_tls_gd(i32 signext %n) nounwind { 91; LARGE-LABEL: test_la_tls_gd: 92; LARGE: pcalau12i [[REG1:\$[a-z0-9]+]], %gd_pc_hi20(gd) 93; LARGE-NEXT: addi.d [[REG2:\$[a-z0-9]+]], $zero, %got_pc_lo12(gd) 94; LARGE-NEXT: lu32i.d [[REG2]], %got64_pc_lo20(gd) 95; LARGE-NEXT: lu52i.d [[REG2]], [[REG2]], %got64_pc_hi12(gd) 96entry: 97 br label %loop 98 99loop: 100 %i = phi i32 [ %inc, %loop ], [ 0, %entry ] 101 %0 = load volatile i32, ptr @gd, align 4 102 %inc = add nuw nsw i32 %i, 1 103 %cmp = icmp slt i32 %inc, %n 104 br i1 %cmp, label %loop, label %ret 105 106ret: 107 ret void 108} 109 110@unspecified = external thread_local global i32 111 112define ptr @test_la_tls_desc() nounwind { 113; LARGEDESC-LABEL: test_la_tls_desc: 114; LARGEDESC: pcalau12i [[REG1:\$[a-z0-9]+]], %desc_pc_hi20(unspecified) 115; LARGEDESC-NEXT: addi.d [[REG2:\$[a-z0-9]+]], $zero, %desc_pc_lo12(unspecified) 116; LARGEDESC-NEXT: lu32i.d [[REG2]], %desc64_pc_lo20(unspecified) 117; LARGEDESC-NEXT: lu52i.d [[REG2]], [[REG2]], %desc64_pc_hi12(unspecified) 118entry: 119 ret ptr @unspecified 120} 121