1ad6fe320SWANG Xuerui; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2*9d4f7f44Swanglei; RUN: llc --mtriple=loongarch32 -mattr=+d --mcpu=generic < %s \ 3ad6fe320SWANG Xuerui; RUN: | FileCheck %s --check-prefix=LA32 4*9d4f7f44Swanglei; RUN: llc --mtriple=loongarch32 -mattr=+d --mcpu=generic-la32 < %s \ 5ad6fe320SWANG Xuerui; RUN: | FileCheck %s --check-prefix=LA32 6*9d4f7f44Swanglei; RUN: llc --mtriple=loongarch64 -mattr=+d --mcpu=generic < %s \ 7ad6fe320SWANG Xuerui; RUN: | FileCheck %s --check-prefix=LA64 8*9d4f7f44Swanglei; RUN: llc --mtriple=loongarch64 -mattr=+d --mcpu=generic-la64 < %s \ 9ad6fe320SWANG Xuerui; RUN: | FileCheck %s --check-prefix=LA64 10ad6fe320SWANG Xuerui 11ad6fe320SWANG Xuerui;; The CPU name "generic" should map to the corresponding concrete names 12ad6fe320SWANG Xuerui;; according to the target triple's bitness. 13ad6fe320SWANG Xueruidefine i64 @f(i64 signext %a, i64 signext %b) { 14ad6fe320SWANG Xuerui; LA32-LABEL: f: 15ad6fe320SWANG Xuerui; LA32: # %bb.0: 16ad6fe320SWANG Xuerui; LA32-NEXT: add.w $a1, $a1, $a3 17ad6fe320SWANG Xuerui; LA32-NEXT: add.w $a2, $a0, $a2 18ad6fe320SWANG Xuerui; LA32-NEXT: sltu $a0, $a2, $a0 19ad6fe320SWANG Xuerui; LA32-NEXT: add.w $a1, $a1, $a0 20ad6fe320SWANG Xuerui; LA32-NEXT: move $a0, $a2 21ad6fe320SWANG Xuerui; LA32-NEXT: ret 22ad6fe320SWANG Xuerui; 23ad6fe320SWANG Xuerui; LA64-LABEL: f: 24ad6fe320SWANG Xuerui; LA64: # %bb.0: 25ad6fe320SWANG Xuerui; LA64-NEXT: add.d $a0, $a0, $a1 26ad6fe320SWANG Xuerui; LA64-NEXT: ret 27ad6fe320SWANG Xuerui %1 = add nsw i64 %a, %b 28ad6fe320SWANG Xuerui ret i64 %1 29ad6fe320SWANG Xuerui} 30