xref: /llvm-project/llvm/test/CodeGen/LoongArch/cpu-name-generic.ll (revision 9d4f7f44b64d87d1068859906f43b7ce03a7388b)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc --mtriple=loongarch32 -mattr=+d --mcpu=generic < %s \
3; RUN:   | FileCheck %s --check-prefix=LA32
4; RUN: llc --mtriple=loongarch32 -mattr=+d --mcpu=generic-la32 < %s \
5; RUN:   | FileCheck %s --check-prefix=LA32
6; RUN: llc --mtriple=loongarch64 -mattr=+d --mcpu=generic < %s \
7; RUN:   | FileCheck %s --check-prefix=LA64
8; RUN: llc --mtriple=loongarch64 -mattr=+d --mcpu=generic-la64 < %s \
9; RUN:   | FileCheck %s --check-prefix=LA64
10
11;; The CPU name "generic" should map to the corresponding concrete names
12;; according to the target triple's bitness.
13define i64 @f(i64 signext %a, i64 signext %b) {
14; LA32-LABEL: f:
15; LA32:       # %bb.0:
16; LA32-NEXT:    add.w $a1, $a1, $a3
17; LA32-NEXT:    add.w $a2, $a0, $a2
18; LA32-NEXT:    sltu $a0, $a2, $a0
19; LA32-NEXT:    add.w $a1, $a1, $a0
20; LA32-NEXT:    move $a0, $a2
21; LA32-NEXT:    ret
22;
23; LA64-LABEL: f:
24; LA64:       # %bb.0:
25; LA64-NEXT:    add.d $a0, $a0, $a1
26; LA64-NEXT:    ret
27  %1 = add nsw i64 %a, %b
28  ret i64 %1
29}
30