1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc --mtriple=loongarch64 -mattr=+d < %s | FileCheck %s 3 4define i64 @lshr40_and255(i64 %a) { 5; CHECK-LABEL: lshr40_and255: 6; CHECK: # %bb.0: 7; CHECK-NEXT: bstrpick.d $a0, $a0, 47, 40 8; CHECK-NEXT: ret 9 %shr = lshr i64 %a, 40 10 %and = and i64 %shr, 255 11 ret i64 %and 12} 13 14define i64 @ashr50_and511(i64 %a) { 15; CHECK-LABEL: ashr50_and511: 16; CHECK: # %bb.0: 17; CHECK-NEXT: bstrpick.d $a0, $a0, 58, 50 18; CHECK-NEXT: ret 19 %shr = ashr i64 %a, 50 20 %and = and i64 %shr, 511 21 ret i64 %and 22} 23 24define i64 @zext_i32_to_i64(i32 %a) { 25; CHECK-LABEL: zext_i32_to_i64: 26; CHECK: # %bb.0: 27; CHECK-NEXT: bstrpick.d $a0, $a0, 31, 0 28; CHECK-NEXT: ret 29 %res = zext i32 %a to i64 30 ret i64 %res 31} 32 33define i64 @and8191(i64 %a) { 34; CHECK-LABEL: and8191: 35; CHECK: # %bb.0: 36; CHECK-NEXT: bstrpick.d $a0, $a0, 12, 0 37; CHECK-NEXT: ret 38 %and = and i64 %a, 8191 39 ret i64 %and 40} 41 42;; Check that andi but not bstrpick.d is generated. 43define i64 @and4095(i64 %a) { 44; CHECK-LABEL: and4095: 45; CHECK: # %bb.0: 46; CHECK-NEXT: andi $a0, $a0, 4095 47; CHECK-NEXT: ret 48 %and = and i64 %a, 4095 49 ret i64 %and 50} 51 52;; (srl (and a, 0xff0), 4) => (BSTRPICK a, 11, 4) 53define i64 @and0xff0_lshr4(i64 %a) { 54; CHECK-LABEL: and0xff0_lshr4: 55; CHECK: # %bb.0: 56; CHECK-NEXT: bstrpick.d $a0, $a0, 11, 4 57; CHECK-NEXT: ret 58 %and = and i64 %a, 4080 59 %shr = lshr i64 %and, 4 60 ret i64 %shr 61} 62 63;; (sra (and a, 0xff0), 5) can also be combined to (BSTRPICK a, 11, 5). 64;; This is because (sra (and a, 0xff0)) would be combined to (srl (and a, 0xff0), 5) 65;; firstly by DAGCombiner::SimplifyDemandedBits. 66define i64 @and4080_ashr5(i64 %a) { 67; CHECK-LABEL: and4080_ashr5: 68; CHECK: # %bb.0: 69; CHECK-NEXT: bstrpick.d $a0, $a0, 11, 5 70; CHECK-NEXT: ret 71 %and = and i64 %a, 4080 72 %shr = ashr i64 %and, 5 73 ret i64 %shr 74} 75 76;; Negative test: the second operand of AND is not a shifted mask 77define i64 @and0xf30_lshr4(i64 %a) { 78; CHECK-LABEL: and0xf30_lshr4: 79; CHECK: # %bb.0: 80; CHECK-NEXT: andi $a0, $a0, 3888 81; CHECK-NEXT: srli.d $a0, $a0, 4 82; CHECK-NEXT: ret 83 %and = and i64 %a, 3888 84 %shr = lshr i64 %and, 4 85 ret i64 %shr 86} 87 88;; Negative test: Shamt < MaskIdx 89define i64 @and0xff0_lshr3(i64 %a) { 90; CHECK-LABEL: and0xff0_lshr3: 91; CHECK: # %bb.0: 92; CHECK-NEXT: andi $a0, $a0, 4080 93; CHECK-NEXT: srli.d $a0, $a0, 3 94; CHECK-NEXT: ret 95 %and = and i64 %a, 4080 96 %shr = lshr i64 %and, 3 97 ret i64 %shr 98} 99