1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc --mtriple=loongarch32 -mattr=+d --filetype=obj --verify-machineinstrs < %s \ 3; RUN: -o /dev/null 2>&1 4; RUN: llc --mtriple=loongarch64 -mattr=+d --filetype=obj --verify-machineinstrs < %s \ 5; RUN: -o /dev/null 2>&1 6; RUN: llc --mtriple=loongarch32 -mattr=+d --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA32 7; RUN: llc --mtriple=loongarch64 -mattr=+d --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA64 8 9define i32 @relax_b18(i32 signext %a, i32 signext %b) { 10; LA32-LABEL: relax_b18: 11; LA32: # %bb.0: 12; LA32-NEXT: beq $a0, $a1, .LBB0_1 13; LA32-NEXT: b .LBB0_2 14; LA32-NEXT: .LBB0_1: # %iftrue 15; LA32-NEXT: ori $a0, $zero, 1 16; LA32-NEXT: #APP 17; LA32-NEXT: .space 1048576 18; LA32-NEXT: #NO_APP 19; LA32-NEXT: ret 20; LA32-NEXT: .LBB0_2: # %iffalse 21; LA32-NEXT: move $a0, $zero 22; LA32-NEXT: ret 23; 24; LA64-LABEL: relax_b18: 25; LA64: # %bb.0: 26; LA64-NEXT: beq $a0, $a1, .LBB0_1 27; LA64-NEXT: b .LBB0_2 28; LA64-NEXT: .LBB0_1: # %iftrue 29; LA64-NEXT: ori $a0, $zero, 1 30; LA64-NEXT: #APP 31; LA64-NEXT: .space 1048576 32; LA64-NEXT: #NO_APP 33; LA64-NEXT: ret 34; LA64-NEXT: .LBB0_2: # %iffalse 35; LA64-NEXT: move $a0, $zero 36; LA64-NEXT: ret 37 %cond = icmp eq i32 %a, %b 38 br i1 %cond, label %iftrue, label %iffalse 39 40iftrue: 41 call void asm sideeffect ".space 1048576", ""() 42 ret i32 1 43 44iffalse: 45 ret i32 0 46} 47 48define i32 @relax_b23(i1 %a) { 49; LA32-LABEL: relax_b23: 50; LA32: # %bb.0: 51; LA32-NEXT: andi $a0, $a0, 1 52; LA32-NEXT: bnez $a0, .LBB1_1 53; LA32-NEXT: b .LBB1_2 54; LA32-NEXT: .LBB1_1: # %iftrue 55; LA32-NEXT: ori $a0, $zero, 1 56; LA32-NEXT: #APP 57; LA32-NEXT: .space 16777216 58; LA32-NEXT: #NO_APP 59; LA32-NEXT: ret 60; LA32-NEXT: .LBB1_2: # %iffalse 61; LA32-NEXT: move $a0, $zero 62; LA32-NEXT: ret 63; 64; LA64-LABEL: relax_b23: 65; LA64: # %bb.0: 66; LA64-NEXT: andi $a0, $a0, 1 67; LA64-NEXT: bnez $a0, .LBB1_1 68; LA64-NEXT: b .LBB1_2 69; LA64-NEXT: .LBB1_1: # %iftrue 70; LA64-NEXT: ori $a0, $zero, 1 71; LA64-NEXT: #APP 72; LA64-NEXT: .space 16777216 73; LA64-NEXT: #NO_APP 74; LA64-NEXT: ret 75; LA64-NEXT: .LBB1_2: # %iffalse 76; LA64-NEXT: move $a0, $zero 77; LA64-NEXT: ret 78 br i1 %a, label %iftrue, label %iffalse 79 80iftrue: 81 call void asm sideeffect ".space 16777216", ""() 82 ret i32 1 83 84iffalse: 85 ret i32 0 86} 87 88define i32 @relax_b28(i1 %a) { 89; LA32-LABEL: relax_b28: 90; LA32: # %bb.0: 91; LA32-NEXT: addi.w $sp, $sp, -16 92; LA32-NEXT: .cfi_def_cfa_offset 16 93; LA32-NEXT: andi $a0, $a0, 1 94; LA32-NEXT: bnez $a0, .LBB2_1 95; LA32-NEXT: # %bb.3: 96; LA32-NEXT: pcalau12i $a0, %pc_hi20(.LBB2_2) 97; LA32-NEXT: addi.w $a0, $a0, %pc_lo12(.LBB2_2) 98; LA32-NEXT: jr $a0 99; LA32-NEXT: .LBB2_1: # %iftrue 100; LA32-NEXT: ori $a0, $zero, 1 101; LA32-NEXT: #APP 102; LA32-NEXT: .space 536870912 103; LA32-NEXT: #NO_APP 104; LA32-NEXT: addi.w $sp, $sp, 16 105; LA32-NEXT: ret 106; LA32-NEXT: .LBB2_2: # %iffalse 107; LA32-NEXT: move $a0, $zero 108; LA32-NEXT: addi.w $sp, $sp, 16 109; LA32-NEXT: ret 110; 111; LA64-LABEL: relax_b28: 112; LA64: # %bb.0: 113; LA64-NEXT: addi.d $sp, $sp, -16 114; LA64-NEXT: .cfi_def_cfa_offset 16 115; LA64-NEXT: andi $a0, $a0, 1 116; LA64-NEXT: bnez $a0, .LBB2_1 117; LA64-NEXT: # %bb.3: 118; LA64-NEXT: pcalau12i $a0, %pc_hi20(.LBB2_2) 119; LA64-NEXT: addi.d $a0, $a0, %pc_lo12(.LBB2_2) 120; LA64-NEXT: jr $a0 121; LA64-NEXT: .LBB2_1: # %iftrue 122; LA64-NEXT: ori $a0, $zero, 1 123; LA64-NEXT: #APP 124; LA64-NEXT: .space 536870912 125; LA64-NEXT: #NO_APP 126; LA64-NEXT: addi.d $sp, $sp, 16 127; LA64-NEXT: ret 128; LA64-NEXT: .LBB2_2: # %iffalse 129; LA64-NEXT: move $a0, $zero 130; LA64-NEXT: addi.d $sp, $sp, 16 131; LA64-NEXT: ret 132 br i1 %a, label %iftrue, label %iffalse 133 134iftrue: 135 call void asm sideeffect ".space 536870912", ""() 136 ret i32 1 137 138iffalse: 139 ret i32 0 140} 141