1; RUN: llc -mtriple=hexagon --filetype=obj < %s -o - | llvm-objdump -d - | FileCheck %s 2 3@g0 = common global double 0.000000e+00, align 8 4@g1 = common global double 0.000000e+00, align 8 5 6; CHECK-LABEL: <f0>: 7; CHECK: r{{[0-9]}}:{{[0-9]}} += vrcmpys(r{{[0-9]}}:{{[0-9]}},r{{[0-9]}}:{{[0-9]}}):<<1:sat:raw:lo 8define double @f0(i32 %a0, i32 %a1) { 9b0: 10 %v0 = load double, ptr @g0, align 8, !tbaa !0 11 %v1 = fptosi double %v0 to i64 12 %v2 = load double, ptr @g1, align 8, !tbaa !0 13 %v3 = fptosi double %v2 to i64 14 %v4 = tail call i64 @llvm.hexagon.M2.vrcmpys.acc.s1(i64 %v1, i64 %v3, i32 %a0) 15 %v5 = sitofp i64 %v4 to double 16 ret double %v5 17} 18 19; Function Attrs: nounwind readnone 20declare i64 @llvm.hexagon.M2.vrcmpys.acc.s1(i64, i64, i32) #0 21 22; CHECK-LABEL: <f1>: 23; CHECK: r{{[0-9]}}:{{[0-9]}} += vrcmpys(r{{[0-9]}}:{{[0-9]}},r{{[0-9]}}:{{[0-9]}}):<<1:sat:raw:hi 24define double @f1(i32 %a0, i32 %a1) { 25b0: 26 %v0 = load double, ptr @g0, align 8, !tbaa !0 27 %v1 = fptosi double %v0 to i64 28 %v2 = load double, ptr @g1, align 8, !tbaa !0 29 %v3 = fptosi double %v2 to i64 30 %v4 = tail call i64 @llvm.hexagon.M2.vrcmpys.acc.s1(i64 %v1, i64 %v3, i32 %a1) 31 %v5 = sitofp i64 %v4 to double 32 ret double %v5 33} 34 35; CHECK-LABEL: <f2>: 36; CHECK: r{{[0-9]}}:{{[0-9]}} = vrcmpys(r{{[0-9]}}:{{[0-9]}},r{{[0-9]}}:{{[0-9]}}):<<1:sat:raw:lo 37define double @f2(i32 %a0, i32 %a1) { 38b0: 39 %v0 = load double, ptr @g1, align 8, !tbaa !0 40 %v1 = fptosi double %v0 to i64 41 %v2 = tail call i64 @llvm.hexagon.M2.vrcmpys.s1(i64 %v1, i32 %a0) 42 %v3 = sitofp i64 %v2 to double 43 ret double %v3 44} 45 46; Function Attrs: nounwind readnone 47declare i64 @llvm.hexagon.M2.vrcmpys.s1(i64, i32) #0 48 49; CHECK-LABEL: <f3>: 50; CHECK: r{{[0-9]}}:{{[0-9]}} = vrcmpys(r{{[0-9]}}:{{[0-9]}},r{{[0-9]}}:{{[0-9]}}):<<1:sat:raw:hi 51define double @f3(i32 %a0, i32 %a1) { 52b0: 53 %v0 = load double, ptr @g1, align 8, !tbaa !0 54 %v1 = fptosi double %v0 to i64 55 %v2 = tail call i64 @llvm.hexagon.M2.vrcmpys.s1(i64 %v1, i32 %a1) 56 %v3 = sitofp i64 %v2 to double 57 ret double %v3 58} 59 60; CHECK-LABEL: <f4>: 61; CHECK: e9a4c2e0 { r0 = vrcmpys(r5:4,r3:2):<<1:rnd:sat:raw:lo } 62; CHECK: e9a4c2c0 { r0 = vrcmpys(r5:4,r3:2):<<1:rnd:sat:raw:hi } 63define void @f4() { 64b0: 65 call void asm sideeffect "r0=vrcmpys(r5:4,r2):<<1:rnd:sat", ""(), !srcloc !4 66 call void asm sideeffect "r0=vrcmpys(r5:4,r3):<<1:rnd:sat", ""(), !srcloc !5 67 ret void 68} 69 70attributes #0 = { nounwind readnone } 71 72!0 = !{!1, !1, i64 0} 73!1 = !{!"double", !2, i64 0} 74!2 = !{!"omnipotent char", !3, i64 0} 75!3 = !{!"Simple C/C++ TBAA"} 76!4 = !{i32 25} 77!5 = !{i32 71} 78