1; RUN: llc -O0 -mtriple=hexagon < %s | FileCheck %s 2 3; Make sure we generate stack alignment. 4; CHECK: [[REG1:r[0-9]*]] = and(r29,#-64) 5; CHECK: vmem([[REG1]]+#2) = 6; CHECK: vmem([[REG1]]+#1) = 7; CHECK: = vmem([[REG1]]+#2) 8; CHECK: = vmem([[REG1]]+#1) 9 10target triple = "hexagon" 11 12@g0 = common global <16 x i32> zeroinitializer, align 64 13 14; Function Attrs: nounwind 15define i32 @f0() #0 { 16b0: 17 %v0 = alloca i32, align 4 18 %v1 = alloca <16 x i32>, align 64 19 %v2 = alloca <16 x i32>, align 64 20 store i32 0, ptr %v0 21 %v3 = call i32 @f1(i8 zeroext 0) 22 %v4 = call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) 23 store <16 x i32> %v4, ptr %v1, align 64 24 %v5 = call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 12) 25 store <16 x i32> %v5, ptr %v2, align 64 26 %v6 = load <16 x i32>, ptr %v1, align 64 27 %v7 = load <16 x i32>, ptr %v2, align 64 28 %v8 = call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v6, <16 x i32> %v7) 29 store <16 x i32> %v8, ptr @g0, align 64 30 call void @f2() 31 ret i32 0 32} 33 34declare i32 @f1(i8 zeroext) #0 35 36; Function Attrs: nounwind readnone 37declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1 38 39; Function Attrs: nounwind readnone 40declare <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32>, <16 x i32>) #1 41 42declare void @f2(...) #0 43 44attributes #0 = { nounwind "target-cpu"="hexagonv65" "target-features"="+hvxv65,+hvx-length64b" } 45attributes #1 = { nounwind readnone } 46