1; RUN: llc -mtriple=hexagon -O0 < %s 2 3; This is a regression test which makes sure that the offset check 4; is available for STRiw_indexed instruction. This is required 5; by 'Hexagon Expand Predicate Spill Code' pass. 6 7define i32 @f0(i32 %a0, i32 %a1) #0 { 8b0: 9 %v0 = alloca i32, align 4 10 %v1 = alloca i32, align 4 11 %v2 = alloca i32, align 4 12 store i32 %a0, ptr %v1, align 4 13 store i32 %a1, ptr %v2, align 4 14 %v3 = load i32, ptr %v1, align 4 15 %v4 = load i32, ptr %v2, align 4 16 %v5 = icmp sgt i32 %v3, %v4 17 br i1 %v5, label %b1, label %b2 18 19b1: ; preds = %b0 20 %v6 = load i32, ptr %v1, align 4 21 %v7 = load i32, ptr %v2, align 4 22 %v8 = add nsw i32 %v6, %v7 23 store i32 %v8, ptr %v0 24 br label %b3 25 26b2: ; preds = %b0 27 %v9 = load i32, ptr %v1, align 4 28 %v10 = load i32, ptr %v2, align 4 29 %v11 = sub nsw i32 %v9, %v10 30 store i32 %v11, ptr %v0 31 br label %b3 32 33b3: ; preds = %b2, %b1 34 %v12 = load i32, ptr %v0 35 ret i32 %v12 36} 37 38attributes #0 = { nounwind "target-cpu"="hexagonv5" } 39