xref: /llvm-project/llvm/test/CodeGen/Hexagon/v6vec_zero.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956)
1; RUN: llc -mtriple=hexagon < %s
2; REQUIRES: asserts
3
4; Test that we do not ICE with a cannot select message when
5; generating a v16i32 constant pool node.
6
7; Function Attrs: nounwind
8define void @f0() #0 {
9b0:
10  br i1 undef, label %b1, label %b2
11
12b1:                                               ; preds = %b1, %b0
13  %v0 = phi i32 [ 0, %b1 ], [ 0, %b0 ]
14  store <16 x i32> zeroinitializer, ptr null, align 64
15  br i1 false, label %b1, label %b2
16
17b2:                                               ; preds = %b1, %b0
18  ret void
19}
20
21attributes #0 = { nounwind "target-cpu"="hexagonv60" }
22