xref: /llvm-project/llvm/test/CodeGen/Hexagon/unordered-fcmp.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956) 
1; RUN: llc -mtriple=hexagon < %s | FileCheck %s
2
3; Check that we generate correct set of instructions for unordered
4; floating-point compares.
5
6; CHECK-LABEL: f0:
7; CHECK-DAG: [[PREG1:p[0-3]+]] = sfcmp.eq(r{{[0-9]+}},r{{[0-9]+}})
8; CHECK-DAG: [[PREG2:p[0-3]+]] = sfcmp.uo(r{{[0-9]+}},r{{[0-9]+}})
9; CHECK: p{{[0-3]+}} = or([[PREG2]],![[PREG1]])
10define float @f0(float %a0, float %a1, float %a2) #0 {
11b0:
12  %v0 = fcmp une float %a0, 0.000000e+00
13  %v1 = select i1 %v0, float %a2, float 0.000000e+00
14  ret float %v1
15}
16
17; CHECK-LABEL: f1:
18; CHECK-DAG: [[PREG1:p[0-3]+]] = sfcmp.ge(r{{[0-9]+}},r{{[0-9]+}})
19; CHECK-DAG: [[PREG2:p[0-3]+]] = sfcmp.uo(r{{[0-9]+}},r{{[0-9]+}})
20; CHECK: p{{[0-3]+}} = or([[PREG2]],[[PREG1]])
21define float @f1(float %a0, float %a1, float %a2) #0 {
22b0:
23  %v0 = fcmp uge float %a0, 0.000000e+00
24  %v1 = select i1 %v0, float %a2, float 0.000000e+00
25  ret float %v1
26}
27
28; CHECK-LABEL: f2:
29; CHECK-DAG: [[PREG1:p[0-3]+]] = sfcmp.gt(r{{[0-9]+}},r{{[0-9]+}})
30; CHECK-DAG: [[PREG2:p[0-3]+]] = sfcmp.uo(r{{[0-9]+}},r{{[0-9]+}})
31; CHECK: p{{[0-3]+}} = or([[PREG2]],[[PREG1]])
32define float @f2(float %a0, float %a1, float %a2) #0 {
33b0:
34  %v0 = fcmp ugt float %a0, 0.000000e+00
35  %v1 = select i1 %v0, float %a2, float 0.000000e+00
36  ret float %v1
37}
38
39; CHECK-LABEL: f3:
40; CHECK-DAG: [[PREG1:p[0-3]+]] = sfcmp.ge(r{{[0-9]+}},r{{[0-9]+}})
41; CHECK-DAG: [[PREG2:p[0-3]+]] = sfcmp.uo(r{{[0-9]+}},r{{[0-9]+}})
42; CHECK: p{{[0-3]+}} = or([[PREG2]],[[PREG1]])
43define float @f3(float %a0, float %a1, float %a2) #0 {
44b0:
45  %v0 = fcmp ule float %a0, 0.000000e+00
46  %v1 = select i1 %v0, float %a2, float 0.000000e+00
47  ret float %v1
48}
49
50; CHECK-LABEL: f4:
51; CHECK-DAG: [[PREG1:p[0-3]+]] = sfcmp.gt(r{{[0-9]+}},r{{[0-9]+}})
52; CHECK-DAG: [[PREG2:p[0-3]+]] = sfcmp.uo(r{{[0-9]+}},r{{[0-9]+}})
53; CHECK: p{{[0-3]+}} = or([[PREG2]],[[PREG1]])
54define float @f4(float %a0, float %a1, float %a2) #0 {
55b0:
56  %v0 = fcmp ult float %a0, 0.000000e+00
57  %v1 = select i1 %v0, float %a2, float 0.000000e+00
58  ret float %v1
59}
60
61attributes #0 = { nounwind "target-cpu"="hexagonv55" }
62