xref: /llvm-project/llvm/test/CodeGen/Hexagon/twoaddressbug.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956)
1; RUN: llc -mtriple=hexagon -O2 < %s
2; REQUIRES: asserts
3
4; This file used to fail with an "UNREACHABLE executed!" in Post-RA pseudo
5; instruction expansion pass due to a bug in the TwoAddressInstructionPass we
6; were not handling sub register indexes when rewriting tied operands.
7
8target triple = "hexagon"
9
10%0 = type { i8, i8, %1, i32, i32, %7, i8, i8, %8, i8, i32, i16, i16, [2500 x i8], i16, i16, i16, ptr, [1024 x i8], i32, i32, i32, i32, i32, i8 }
11%1 = type { i8, %2, i8, i8, i32 }
12%2 = type { %3 }
13%3 = type { i8, [256 x i8], %4, i8, i16, i32 }
14%4 = type { %5 }
15%5 = type { %6 }
16%6 = type { [2 x i64] }
17%7 = type { i32, i8 }
18%8 = type { %7, i32, i32, %1 }
19%9 = type { %10, ptr }
20%10 = type { i16, i16, i32 }
21%11 = type { i8, i32 }
22
23@g0 = external hidden global [2 x %0], align 8
24@g1 = external hidden constant %9, align 4
25@g2 = external hidden constant %9, align 4
26@g3 = external hidden constant %9, align 4
27@g4 = external hidden constant %9, align 4
28
29; Function Attrs: optsize
30declare void @f0(ptr, i32, i32, i32) #0
31
32; Function Attrs: nounwind optsize ssp
33define hidden fastcc void @f1(i64 %a0, i8 zeroext %a1, i8 zeroext %a2) #1 {
34b0:
35  %v0 = alloca %11, align 4
36  %v1 = icmp ne i8 %a1, 0
37  %v2 = trunc i64 %a0 to i32
38  br i1 %v1, label %b1, label %b4
39
40b1:                                               ; preds = %b0
41  call void @f0(ptr @g1, i32 %v2, i32 0, i32 0) #2
42  %v3 = getelementptr inbounds [2 x %0], ptr @g0, i32 0, i32 %v2, i32 7
43  store i8 1, ptr %v3, align 1
44  %v4 = icmp eq i8 %a2, 0
45  br i1 %v4, label %b4, label %b2
46
47b2:                                               ; preds = %b1
48  store i8 0, ptr %v0, align 4
49  %v6 = getelementptr inbounds %11, ptr %v0, i32 0, i32 1
50  store i32 0, ptr %v6, align 4
51  %v7 = getelementptr inbounds [2 x %0], ptr @g0, i32 0, i32 %v2, i32 3
52  %v8 = load i32, ptr %v7, align 8
53  %v9 = getelementptr inbounds [2 x %0], ptr @g0, i32 0, i32 %v2, i32 4
54  %v10 = load i32, ptr %v9, align 4
55  %v11 = getelementptr inbounds [2 x %0], ptr @g0, i32 0, i32 %v2, i32 19
56  %v12 = load i32, ptr %v11, align 4
57  %v13 = call zeroext i8 @f2(i64 %a0, i32 %v8, i32 %v10, i32 %v12, i8 zeroext 0, ptr %v0) #2
58  %v14 = icmp eq i8 %v13, 0
59  br i1 %v14, label %b4, label %b3
60
61b3:                                               ; preds = %b2
62  %v15 = zext i8 %v13 to i32
63  call void @f0(ptr @g2, i32 %v15, i32 %v2, i32 0) #2
64  br label %b4
65
66b4:                                               ; preds = %b3, %b2, %b1, %b0
67  %v16 = getelementptr inbounds [2 x %0], ptr @g0, i32 0, i32 %v2, i32 1
68  %v17 = load i8, ptr %v16, align 1
69  %v18 = zext i8 %v17 to i32
70  switch i32 %v18, label %b14 [
71    i32 2, label %b11
72    i32 1, label %b5
73    i32 4, label %b8
74    i32 3, label %b11
75  ]
76
77b5:                                               ; preds = %b4
78  call void @f0(ptr @g3, i32 %v2, i32 0, i32 0) #2
79  br i1 %v1, label %b7, label %b6
80
81b6:                                               ; preds = %b5
82  call fastcc void @f3(i64 %a0, i8 zeroext 0, i8 zeroext 1, i32 1) #0
83  br label %b14
84
85b7:                                               ; preds = %b5
86  call fastcc void @f3(i64 %a0, i8 zeroext 0, i8 zeroext 0, i32 1) #0
87  br label %b14
88
89b8:                                               ; preds = %b4
90  call void @f0(ptr @g4, i32 %v2, i32 0, i32 0) #2
91  %v19 = getelementptr inbounds [2 x %0], ptr @g0, i32 0, i32 %v2, i32 6
92  store i8 1, ptr %v19, align 8
93  br i1 %v1, label %b10, label %b9
94
95b9:                                               ; preds = %b8
96  call fastcc void @f3(i64 %a0, i8 zeroext 0, i8 zeroext 1, i32 1) #0
97  br label %b14
98
99b10:                                              ; preds = %b8
100  call fastcc void @f3(i64 %a0, i8 zeroext 0, i8 zeroext 0, i32 1) #0
101  br label %b14
102
103b11:                                              ; preds = %b4, %b4
104  br i1 %v1, label %b13, label %b12
105
106b12:                                              ; preds = %b11
107  call fastcc void @f3(i64 %a0, i8 zeroext 0, i8 zeroext 1, i32 1) #0
108  br label %b14
109
110b13:                                              ; preds = %b11
111  call fastcc void @f3(i64 %a0, i8 zeroext 0, i8 zeroext 0, i32 1) #0
112  br label %b14
113
114b14:                                              ; preds = %b13, %b12, %b10, %b9, %b7, %b6, %b4
115  ret void
116}
117
118; Function Attrs: optsize
119declare zeroext i8 @f2(i64, i32, i32, i32, i8 zeroext, ptr) #0
120
121; Function Attrs: nounwind optsize ssp
122declare hidden fastcc void @f3(i64, i8 zeroext, i8 zeroext, i32) #1
123
124attributes #0 = { optsize }
125attributes #1 = { nounwind optsize ssp }
126attributes #2 = { nounwind optsize }
127