1; RUN: llc -mtriple=hexagon -mcpu=hexagonv67t < %s | FileCheck %s 2; RUN: llc -mtriple=hexagon -mcpu=hexagonv65 < %s | FileCheck --check-prefix=CHECK-BIG %s 3 4; Test that the tiny core architecture generates 3 slot packets at most and 5; a single load/store per packet at most. 6 7; CHECK: loop0(.LBB0_[[LOOP:.]], 8; CHECK: .LBB0_[[LOOP]]: 9; CHECK: { 10; CHECK-NEXT: mpy 11; CHECK-NEXT: combine 12; CHECK-NEXT: memw 13; CHECK-NEXT: } 14; CHECK: memw 15; CHECK: } :endloop0 16 17; Test the loop contains a single packet with 4 instructions. 18; CHECK-BIG: loop0(.LBB0_[[LOOP:.]], 19; CHECK-BIG: .LBB0_[[LOOP]]: 20; CHECK-BIG: { 21; CHECK-BIG: += mpyi 22; CHECK-BIG-NEXT: = combine 23; CHECK-BIG-NEXT: = memw 24; CHECK-BIG-NEXT: = memw 25; CHECK-BIG-NEXT: } :endloop0 26 27define i32 @test(ptr noalias nocapture readonly %a, ptr noalias nocapture readonly %b, i32 %n) local_unnamed_addr #0 { 28entry: 29 %cmp8 = icmp sgt i32 %n, 0 30 br i1 %cmp8, label %for.body, label %for.end 31 32for.body: 33 %sum.010 = phi i32 [ %add, %for.body ], [ 0, %entry ] 34 %arrayidx.phi = phi ptr [ %arrayidx.inc, %for.body ], [ %a, %entry ] 35 %arrayidx1.phi = phi ptr [ %arrayidx1.inc, %for.body ], [ %b, %entry ] 36 %i.09 = phi i32 [ %inc, %for.body ], [ 0, %entry ] 37 %0 = load i32, ptr %arrayidx.phi, align 4 38 %1 = load i32, ptr %arrayidx1.phi, align 4 39 %mul = mul nsw i32 %1, %0 40 %add = add nsw i32 %mul, %sum.010 41 %inc = add nuw nsw i32 %i.09, 1 42 %exitcond = icmp eq i32 %inc, %n 43 %arrayidx.inc = getelementptr i32, ptr %arrayidx.phi, i32 1 44 %arrayidx1.inc = getelementptr i32, ptr %arrayidx1.phi, i32 1 45 br i1 %exitcond, label %for.end, label %for.body 46 47for.end: 48 %sum.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ] 49 ret i32 %sum.0.lcssa 50} 51 52