xref: /llvm-project/llvm/test/CodeGen/Hexagon/testbits.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956) 
1; RUN: llc -mtriple=hexagon < %s | FileCheck %s
2
3; CHECK-LABEL: f0:
4; CHECK: p0 = bitsset(r0,r1)
5define i32 @f0(i32 %a0, i32 %a1) #0 {
6b0:
7  %v0 = and i32 %a0, %a1
8  %v1 = icmp eq i32 %v0, %a1
9  %v2 = select i1 %v1, i32 2, i32 3
10  ret i32 %v2
11}
12
13; CHECK-LABEL: f1:
14; CHECK: p0 = bitsclr(r0,r1)
15define i32 @f1(i32 %a0, i32 %a1) #0 {
16b0:
17  %v0 = and i32 %a0, %a1
18  %v1 = icmp eq i32 %v0, 0
19  %v2 = select i1 %v1, i32 2, i32 3
20  ret i32 %v2
21}
22
23; CHECK-LABEL: f2:
24; CHECK: p0 = bitsclr(r0,#37)
25define i32 @f2(i32 %a0) #0 {
26b0:
27  %v0 = and i32 %a0, 37
28  %v1 = icmp eq i32 %v0, 0
29  %v2 = select i1 %v1, i32 2, i32 3
30  ret i32 %v2
31}
32
33attributes #0 = { nounwind "target-cpu"="hexagonv55" }
34