xref: /llvm-project/llvm/test/CodeGen/Hexagon/tc_duplex_asm.ll (revision 806761a7629df268c8aed49657aeccffa6bca449)
1; RUN: llc -mtriple=hexagon -mattr=+duplex -mcpu=hexagonv67t -filetype=obj < %s \
2; RUN: -o - | llvm-objdump -d - | FileCheck %s
3
4; Check that we generate two memory operations in tiny core if duplexes
5; are enabled.
6
7; CHECK: memw{{.*}};{{.*}}memw
8; CHECK: memw{{.*}};{{.*}}memw
9
10define i32 @test(ptr noalias nocapture readonly %a, ptr noalias nocapture readonly %b, i32 %n) local_unnamed_addr #0 {
11entry:
12  %0 = load i32, ptr %a, align 4
13  %1 = load i32, ptr %b, align 4
14  %mul = mul nsw i32 %1, %0
15  %arrayidx.inc = getelementptr i32, ptr %a, i32 1
16  %arrayidx1.inc = getelementptr i32, ptr %b, i32 1
17  %2 = load i32, ptr %arrayidx.inc, align 4
18  %3 = load i32, ptr %arrayidx1.inc, align 4
19  %mul.1 = mul nsw i32 %3, %2
20  %add.1 = add nsw i32 %mul.1, %mul
21  ret i32 %add.1
22}
23