1; RUN: llc -mtriple=hexagon -O3 < %s 2; REQUIRES: asserts 3 4; Test that we generate the correct names for Phis when there is 5; a Phi that references a Phi that references another Phi. For example, 6; v6 = phi(v1, v9) 7; v7 = phi(v0, v6) 8; v8 = phi(v2, v7) 9 10; Function Attrs: nounwind 11define void @f0(ptr noalias nocapture readonly %a0, i32 %a1, i32 %a2, ptr noalias nocapture %a3, i32 %a4) #0 { 12b0: 13 %v0 = add i32 %a1, -1 14 %v2 = getelementptr inbounds i8, ptr %a0, i32 undef 15 br i1 undef, label %b1, label %b4 16 17b1: ; preds = %b1, %b0 18 br i1 undef, label %b1, label %b2 19 20b2: ; preds = %b1 21 %v4 = getelementptr inbounds i8, ptr %a0, i32 undef 22 br label %b3 23 24b3: ; preds = %b3, %b2 25 %v5 = phi ptr [ %v10, %b3 ], [ %a3, %b2 ] 26 %v6 = phi ptr [ %v25, %b3 ], [ %v4, %b2 ] 27 %v7 = phi ptr [ %v6, %b3 ], [ %v2, %b2 ] 28 %v8 = phi ptr [ %v7, %b3 ], [ %a0, %b2 ] 29 %v9 = phi i32 [ %v26, %b3 ], [ 1, %b2 ] 30 %v10 = getelementptr inbounds i8, ptr %v5, i32 %a4 31 %v11 = getelementptr inbounds i8, ptr %v8, i32 -1 32 %v12 = load i8, ptr %v11, align 1, !tbaa !0 33 %v13 = zext i8 %v12 to i32 34 %v14 = add nuw nsw i32 %v13, 0 35 %v15 = add nuw nsw i32 %v14, 0 36 %v16 = add nuw nsw i32 %v15, 0 37 %v17 = load i8, ptr %v6, align 1, !tbaa !0 38 %v18 = zext i8 %v17 to i32 39 %v19 = add nuw nsw i32 %v16, %v18 40 %v20 = add nuw nsw i32 %v19, 0 41 %v21 = mul nsw i32 %v20, 7282 42 %v22 = add nsw i32 %v21, 32768 43 %v23 = lshr i32 %v22, 16 44 %v24 = trunc i32 %v23 to i8 45 store i8 %v24, ptr %v10, align 1, !tbaa !0 46 %v25 = getelementptr inbounds i8, ptr %v6, i32 %a2 47 %v26 = add i32 %v9, 1 48 %v27 = icmp eq i32 %v26, %v0 49 br i1 %v27, label %b4, label %b3 50 51b4: ; preds = %b3, %b0 52 ret void 53} 54 55attributes #0 = { nounwind "target-cpu"="hexagonv55" } 56 57!0 = !{!1, !1, i64 0} 58!1 = !{!"omnipotent char", !2, i64 0} 59!2 = !{!"Simple C/C++ TBAA"} 60