1; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 < %s -pipeliner-experimental-cg=true | FileCheck %s 2 3; Test that the pipeliner schedules a store before the load in which there is a 4; loop carried dependence. Previously, the loop carried dependence wasn't added 5; and the load from iteration n was scheduled prior to the store from iteration 6; n-1. 7 8; CHECK: loop0(.LBB0_[[LOOP:.]], 9; CHECK: .LBB0_[[LOOP]]: 10; CHECK: memh({{.*}}) = 11; CHECK: = memuh({{.*}}) 12; CHECK: endloop0 13 14%s.0 = type { i16, i16 } 15 16; Function Attrs: nounwind 17define void @f0() local_unnamed_addr #0 { 18b0: 19 br label %b1 20 21b1: ; preds = %b1, %b0 22 %v0 = phi i32 [ 0, %b0 ], [ %v22, %b1 ] 23 %v1 = load ptr, ptr undef, align 4 24 %v3 = load i16, ptr %v1, align 2 25 %v4 = add i16 0, %v3 26 %v5 = add i16 %v4, 0 27 %v6 = add i16 %v5, 0 28 %v7 = add i16 %v6, 0 29 %v8 = add i16 %v7, 0 30 %v9 = add i16 %v8, 0 31 %v10 = add i16 %v9, 0 32 %v11 = add i16 %v10, 0 33 %v12 = add i16 %v11, 0 34 %v13 = add i16 %v12, 0 35 %v14 = add i16 %v13, 0 36 %v15 = add i16 %v14, 0 37 %v16 = add i16 %v15, 0 38 %v17 = add i16 %v16, 0 39 %v18 = add i16 %v17, 0 40 %v19 = add i16 %v18, 0 41 %v20 = load ptr, ptr undef, align 4 42 store i16 %v19, ptr undef, align 2 43 %v21 = getelementptr inbounds %s.0, ptr %v20, i32 0, i32 1 44 store i16 0, ptr %v21, align 2 45 %v22 = add nuw nsw i32 %v0, 1 46 %v23 = icmp eq i32 %v22, 6 47 br i1 %v23, label %b2, label %b1 48 49b2: ; preds = %b1 50 ret void 51} 52 53attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" } 54