xref: /llvm-project/llvm/test/CodeGen/Hexagon/swp-listen-loop3.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956)
1; RUN: llc -mtriple=hexagon -pipeliner-ignore-recmii -pipeliner-max-stages=2 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s
2
3; This is a loop we pipeline to three packets, though we could do bettter.
4
5; CHECK: loop0(.LBB0_[[LOOP:.]],
6; CHECK: .LBB0_[[LOOP]]:
7; CHECK: {
8; CHECK: }
9; CHECK: {
10; CHECK: }
11; CHECK: {
12; CHECK: }{{[ \t]*}}:endloop0
13
14; Function Attrs: nounwind
15define void @f0(ptr nocapture %a0, i16 signext %a1) #0 {
16b0:
17  %v0 = sext i16 %a1 to i32
18  %v1 = add i32 %v0, -1
19  %v2 = icmp sgt i32 %v1, 0
20  br i1 %v2, label %b1, label %b4
21
22b1:                                               ; preds = %b0
23  %v3 = getelementptr i32, ptr %a0, i32 %v1
24  %v4 = load i32, ptr %v3, align 4
25  br label %b2
26
27b2:                                               ; preds = %b2, %b1
28  %v5 = phi i32 [ %v16, %b2 ], [ %v1, %b1 ]
29  %v6 = phi i32 [ %v5, %b2 ], [ %v0, %b1 ]
30  %v7 = phi i32 [ %v10, %b2 ], [ %v4, %b1 ]
31  %v8 = add nsw i32 %v6, -2
32  %v9 = getelementptr inbounds i32, ptr %a0, i32 %v8
33  %v10 = load i32, ptr %v9, align 4, !tbaa !0
34  %v11 = tail call i64 @llvm.hexagon.M2.dpmpyss.s0(i32 %v10, i32 7946)
35  %v12 = tail call i64 @llvm.hexagon.S2.asl.r.p(i64 %v11, i32 -13)
36  %v13 = getelementptr inbounds i32, ptr %a0, i32 %v5
37  %v14 = tail call i32 @llvm.hexagon.A2.sat(i64 %v12)
38  %v15 = tail call i32 @llvm.hexagon.A2.subsat(i32 %v7, i32 %v14)
39  store i32 %v15, ptr %v13, align 4, !tbaa !0
40  %v16 = add nsw i32 %v5, -1
41  %v17 = icmp sgt i32 %v16, 0
42  br i1 %v17, label %b2, label %b3
43
44b3:                                               ; preds = %b2
45  br label %b4
46
47b4:                                               ; preds = %b3, %b0
48  ret void
49}
50
51; Function Attrs: nounwind readnone
52declare i64 @llvm.hexagon.S2.asl.r.p(i64, i32) #1
53
54; Function Attrs: nounwind readnone
55declare i64 @llvm.hexagon.M2.dpmpyss.s0(i32, i32) #1
56
57; Function Attrs: nounwind readnone
58declare i32 @llvm.hexagon.A2.subsat(i32, i32) #1
59
60; Function Attrs: nounwind readnone
61declare i32 @llvm.hexagon.A2.sat(i64) #1
62
63attributes #0 = { nounwind "target-cpu"="hexagonv55" }
64attributes #1 = { nounwind readnone }
65
66!0 = !{!1, !1, i64 0}
67!1 = !{!"int", !2}
68!2 = !{!"omnipotent char", !3}
69!3 = !{!"Simple C/C++ TBAA"}
70