xref: /llvm-project/llvm/test/CodeGen/Hexagon/swp-conv3x3-nested.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956) 
1; RUN: llc -mtriple=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s
2
3; This version of the conv3x3 test has both loops. This test checks that the
4; inner loop has 14 packets.
5
6; CHECK: loop0(.LBB0_[[LOOP:.]],
7; CHECK: .LBB0_[[LOOP]]:
8; CHECK: }
9; CHECK: }
10; CHECK: }
11; CHECK: }
12; CHECK: }
13; CHECK: }
14; CHECK: }
15; CHECK: }
16; CHECK: }
17; CHECK: }
18; CHECK: }
19; CHECK: }
20; CHECK: }
21; CHECK-NOT: }
22; CHECK: }{{[ \t]*}}:endloop0
23
24declare <16 x i32> @llvm.hexagon.V6.vd0() #0
25declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #0
26declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #0
27declare <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32>, i32, i32) #0
28declare <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32>, <32 x i32>, i32, i32) #0
29declare <16 x i32> @llvm.hexagon.V6.vasrwhsat(<16 x i32>, <16 x i32>, i32) #0
30declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #0
31declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #0
32declare <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32>, <16 x i32>) #0
33declare <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32>, <16 x i32>, i32) #0
34
35define void @f0(ptr noalias nocapture readonly %a0, i32 %a1, i32 %a2, i32 %a3, ptr noalias nocapture readonly %a4, i32 %a5, ptr noalias nocapture %a6) local_unnamed_addr #1 {
36b0:
37  %v0 = add nsw i32 %a3, -1
38  %v1 = icmp sgt i32 %a3, 2
39  br i1 %v1, label %b1, label %b6
40
41b1:                                               ; preds = %b0
42  %v2 = getelementptr inbounds i8, ptr %a6, i32 %a1
43  %v3 = getelementptr inbounds i8, ptr %a0, i32 %a1
44  %v5 = load i32, ptr %a4, align 4, !tbaa !1, !alias.scope !5, !noalias !8
45  %v6 = getelementptr inbounds i8, ptr %a4, i32 4
46  %v8 = load i32, ptr %v6, align 4, !tbaa !1, !alias.scope !5, !noalias !8
47  %v9 = getelementptr inbounds i8, ptr %a4, i32 8
48  %v11 = load i32, ptr %v9, align 4, !tbaa !1, !alias.scope !5, !noalias !8
49  %v12 = sub i32 0, %a1
50  %v13 = shl nsw i32 %a1, 1
51  %v14 = tail call <16 x i32> @llvm.hexagon.V6.vd0() #2
52  %v15 = icmp sgt i32 %a2, 0
53  br label %b2
54
55b2:                                               ; preds = %b5, %b1
56  %v16 = phi ptr [ %v2, %b1 ], [ %v102, %b5 ]
57  %v17 = phi ptr [ %v3, %b1 ], [ %v21, %b5 ]
58  %v18 = phi i32 [ 1, %b1 ], [ %v103, %b5 ]
59  %v19 = getelementptr inbounds i8, ptr %v17, i32 %v12
60  %v20 = getelementptr inbounds i8, ptr %v17, i32 %a1
61  %v21 = getelementptr inbounds i8, ptr %v17, i32 %v13
62  br i1 %v15, label %b3, label %b5
63
64b3:                                               ; preds = %b2
65  %v23 = load <16 x i32>, ptr %v21, align 64, !tbaa !11, !alias.scope !12, !noalias !13
66  %v24 = getelementptr inbounds i8, ptr %v21, i32 64
67  %v27 = load <16 x i32>, ptr %v20, align 64, !tbaa !11, !alias.scope !12, !noalias !13
68  %v28 = getelementptr inbounds i8, ptr %v20, i32 64
69  %v31 = load <16 x i32>, ptr %v17, align 64, !tbaa !11, !alias.scope !12, !noalias !13
70  %v32 = getelementptr inbounds i8, ptr %v17, i32 64
71  %v35 = load <16 x i32>, ptr %v19, align 64, !tbaa !11, !alias.scope !12, !noalias !13
72  %v36 = getelementptr inbounds i8, ptr %v19, i32 64
73  %v38 = getelementptr inbounds i8, ptr %v16, i32 %a1
74  br label %b4
75
76b4:                                               ; preds = %b4, %b3
77  %v41 = phi ptr [ %v38, %b3 ], [ %v99, %b4 ]
78  %v42 = phi ptr [ %v16, %b3 ], [ %v84, %b4 ]
79  %v43 = phi ptr [ %v24, %b3 ], [ %v60, %b4 ]
80  %v44 = phi ptr [ %v28, %b3 ], [ %v58, %b4 ]
81  %v45 = phi ptr [ %v32, %b3 ], [ %v56, %b4 ]
82  %v46 = phi ptr [ %v36, %b3 ], [ %v54, %b4 ]
83  %v47 = phi i32 [ %a2, %b3 ], [ %v100, %b4 ]
84  %v48 = phi <16 x i32> [ %v35, %b3 ], [ %v55, %b4 ]
85  %v49 = phi <16 x i32> [ %v31, %b3 ], [ %v57, %b4 ]
86  %v50 = phi <16 x i32> [ %v27, %b3 ], [ %v59, %b4 ]
87  %v51 = phi <16 x i32> [ %v23, %b3 ], [ %v61, %b4 ]
88  %v52 = phi <16 x i32> [ %v14, %b3 ], [ %v82, %b4 ]
89  %v53 = phi <16 x i32> [ %v14, %b3 ], [ %v97, %b4 ]
90  %v54 = getelementptr inbounds <16 x i32>, ptr %v46, i32 1
91  %v55 = load <16 x i32>, ptr %v46, align 64, !tbaa !11, !alias.scope !12, !noalias !13
92  %v56 = getelementptr inbounds <16 x i32>, ptr %v45, i32 1
93  %v57 = load <16 x i32>, ptr %v45, align 64, !tbaa !11, !alias.scope !12, !noalias !13
94  %v58 = getelementptr inbounds <16 x i32>, ptr %v44, i32 1
95  %v59 = load <16 x i32>, ptr %v44, align 64, !tbaa !11, !alias.scope !12, !noalias !13
96  %v60 = getelementptr inbounds <16 x i32>, ptr %v43, i32 1
97  %v61 = load <16 x i32>, ptr %v43, align 64, !tbaa !11, !alias.scope !12, !noalias !13
98  %v62 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v55, <16 x i32> %v48, i32 4) #2
99  %v63 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v57, <16 x i32> %v49, i32 4) #2
100  %v64 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v59, <16 x i32> %v50, i32 4) #2
101  %v65 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v61, <16 x i32> %v51, i32 4) #2
102  %v66 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v62, <16 x i32> %v48) #2
103  %v67 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v63, <16 x i32> %v49) #2
104  %v68 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v64, <16 x i32> %v50) #2
105  %v69 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v65, <16 x i32> %v51) #2
106  %v70 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v66, i32 %v5, i32 0) #2
107  %v71 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v66, i32 %v5, i32 1) #2
108  %v72 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v70, <32 x i32> %v67, i32 %v8, i32 0) #2
109  %v73 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v71, <32 x i32> %v67, i32 %v8, i32 1) #2
110  %v74 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v72, <32 x i32> %v68, i32 %v11, i32 0) #2
111  %v75 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v73, <32 x i32> %v68, i32 %v11, i32 1) #2
112  %v76 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v75) #2
113  %v77 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v75) #2
114  %v78 = tail call <16 x i32> @llvm.hexagon.V6.vasrwhsat(<16 x i32> %v76, <16 x i32> %v77, i32 %a5) #2
115  %v79 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v74) #2
116  %v80 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v74) #2
117  %v81 = tail call <16 x i32> @llvm.hexagon.V6.vasrwhsat(<16 x i32> %v79, <16 x i32> %v80, i32 %a5) #2
118  %v82 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %v78, <16 x i32> %v81) #2
119  %v83 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v82, <16 x i32> %v52, i32 1) #2
120  %v84 = getelementptr inbounds <16 x i32>, ptr %v42, i32 1
121  store <16 x i32> %v83, ptr %v42, align 64, !tbaa !11, !alias.scope !14, !noalias !15
122  %v85 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v67, i32 %v5, i32 0) #2
123  %v86 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v67, i32 %v5, i32 1) #2
124  %v87 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v85, <32 x i32> %v68, i32 %v8, i32 0) #2
125  %v88 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v86, <32 x i32> %v68, i32 %v8, i32 1) #2
126  %v89 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v87, <32 x i32> %v69, i32 %v11, i32 0) #2
127  %v90 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v88, <32 x i32> %v69, i32 %v11, i32 1) #2
128  %v91 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v90) #2
129  %v92 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v90) #2
130  %v93 = tail call <16 x i32> @llvm.hexagon.V6.vasrwhsat(<16 x i32> %v91, <16 x i32> %v92, i32 %a5) #2
131  %v94 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v89) #2
132  %v95 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v89) #2
133  %v96 = tail call <16 x i32> @llvm.hexagon.V6.vasrwhsat(<16 x i32> %v94, <16 x i32> %v95, i32 %a5) #2
134  %v97 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %v93, <16 x i32> %v96) #2
135  %v98 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v97, <16 x i32> %v53, i32 1) #2
136  %v99 = getelementptr inbounds <16 x i32>, ptr %v41, i32 1
137  store <16 x i32> %v98, ptr %v41, align 64, !tbaa !11, !alias.scope !14, !noalias !15
138  %v100 = add nsw i32 %v47, -64
139  %v101 = icmp sgt i32 %v47, 64
140  br i1 %v101, label %b4, label %b5
141
142b5:                                               ; preds = %b4, %b2
143  %v102 = getelementptr inbounds i8, ptr %v16, i32 %v13
144  %v103 = add nuw nsw i32 %v18, 2
145  %v104 = icmp slt i32 %v103, %v0
146  br i1 %v104, label %b2, label %b6
147
148b6:                                               ; preds = %b5, %b0
149  ret void
150}
151
152attributes #0 = { nounwind readnone }
153attributes #1 = { nounwind "target-cpu"="hexagonv62" "target-features"="+hvx-length64b,+hvxv62" }
154attributes #2 = { nounwind }
155
156!llvm.module.flags = !{!0}
157
158!0 = !{i32 1, !"wchar_size", i32 4}
159!1 = !{!2, !2, i64 0}
160!2 = !{!"int", !3, i64 0}
161!3 = !{!"omnipotent char", !4, i64 0}
162!4 = !{!"Simple C/C++ TBAA"}
163!5 = !{!6}
164!6 = distinct !{!6, !7, !"x: %a"}
165!7 = distinct !{!7, !"x"}
166!8 = !{!9, !10}
167!9 = distinct !{!9, !7, !"x: %b"}
168!10 = distinct !{!10, !7, !"x: %c"}
169!11 = !{!3, !3, i64 0}
170!12 = !{!9}
171!13 = !{!6, !10}
172!14 = !{!10}
173!15 = !{!9, !6}
174