1; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s 2; RUN: llc -mtriple=hexagon -mcpu=hexagonv62 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck --check-prefix=CHECK-V62 %s 3; RUN: llc -mtriple=hexagon -mcpu=hexagonv65 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck --check-prefix=CHECK-V65 %s 4 5; 6; Make sure we pipeline the loop and that we generate the correct 7; base+offset values for the loads. 8 9; CHECK: loop0(.LBB0_[[LOOP:.]], 10; CHECK: .LBB0_[[LOOP]]: 11; CHECK: r{{[0-9]+}} = memw([[REG1:(r[0-9]+)]]+#{{[0,4]}}) 12; CHECK: r{{[0-9]+}} = memw([[REG1]]++#4) 13; CHECK: }{{[ \t]*}}:endloop 14; CHECK-V62-NOT: }{{[ \t]*}}:mem_noshuf 15; CHECK-V65: }{{[ \t]*}}:mem_noshuf 16 17; Function Attrs: nounwind 18define i32 @f0(ptr %a0) #0 { 19b0: 20 br label %b1 21 22b1: ; preds = %b1, %b0 23 %v0 = phi i32 [ %v7, %b1 ], [ 0, %b0 ] 24 %v1 = getelementptr inbounds ptr, ptr %a0, i32 %v0 25 %v2 = load ptr, ptr %v1, align 4 26 store i32 0, ptr %v2, align 4 27 %v4 = load ptr, ptr %v1, align 4 28 %v5 = getelementptr inbounds i8, ptr %v4, i32 8 29 store i32 0, ptr %v5, align 4 30 %v7 = add nsw i32 %v0, 1 31 %v8 = icmp eq i32 %v7, 2 32 br i1 %v8, label %b2, label %b1 33 34b2: ; preds = %b1 35 ret i32 %v7 36} 37 38attributes #0 = { nounwind } 39