xref: /llvm-project/llvm/test/CodeGen/Hexagon/store-imm-stack-object.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956) 
1; RUN: llc -mtriple=hexagon < %s | FileCheck %s
2
3target triple = "hexagon"
4
5; CHECK-LABEL: test1:
6; CHECK-DAG: memw(r29+#12) = ##875770417
7; CHECK-DAG: memw(r29+#8) = #51
8; CHECK-DAG: memh(r29+#6) = #50
9; CHECK-DAG: memb(r29+#5) = #49
10define void @test1() {
11b0:
12  %v1 = alloca [1 x i8], align 1
13  %v2 = alloca i16, align 2
14  %v3 = alloca i32, align 4
15  %v4 = alloca i32, align 4
16  call void @llvm.lifetime.start(i64 1, ptr %v1)
17  store i8 49, ptr %v1, align 1
18  call void @llvm.lifetime.start(i64 2, ptr %v2)
19  store i16 50, ptr %v2, align 2
20  call void @llvm.lifetime.start(i64 4, ptr %v3)
21  store i32 51, ptr %v3, align 4
22  call void @llvm.lifetime.start(i64 4, ptr %v4)
23  store i32 875770417, ptr %v4, align 4
24  call void @test4(ptr %v1, ptr %v2, ptr %v3, ptr %v4)
25  call void @llvm.lifetime.end(i64 4, ptr %v4)
26  call void @llvm.lifetime.end(i64 4, ptr %v3)
27  call void @llvm.lifetime.end(i64 2, ptr %v2)
28  call void @llvm.lifetime.end(i64 1, ptr %v1)
29  ret void
30}
31
32; CHECK-LABEL: test2:
33; CHECK-DAG: memw(r29+#8) = #51
34; CHECK-DAG: memh(r29+#6) = r{{[0-9]+}}
35; CHECK-DAG: memb(r29+#5) = r{{[0-9]+}}
36define void @test2() {
37b0:
38  %v1 = alloca [1 x i8], align 1
39  %v2 = alloca i16, align 2
40  %v3 = alloca i32, align 4
41  %v4 = alloca i32, align 4
42  %v5 = alloca [100 x i8], align 8
43  %v6 = alloca [101 x i8], align 8
44  call void @llvm.lifetime.start(i64 1, ptr %v1)
45  store i8 49, ptr %v1, align 1
46  call void @llvm.lifetime.start(i64 2, ptr %v2)
47  store i16 50, ptr %v2, align 2
48  call void @llvm.lifetime.start(i64 4, ptr %v3)
49  store i32 51, ptr %v3, align 4
50  call void @llvm.lifetime.start(i64 4, ptr %v4)
51  store i32 875770417, ptr %v4, align 4
52  call void @llvm.lifetime.start(i64 100, ptr %v5)
53  call void @llvm.memset.p0.i32(ptr align 8 %v5, i8 0, i32 100, i1 false)
54  store i8 50, ptr %v5, align 8
55  call void @llvm.lifetime.start(i64 101, ptr %v6)
56  call void @llvm.memset.p0.i32(ptr align 8 %v6, i8 0, i32 101, i1 false)
57  store i8 49, ptr %v6, align 8
58  call void @test3(ptr %v1, ptr %v2, ptr %v3, ptr %v4, ptr %v5, ptr %v6)
59  call void @llvm.lifetime.end(i64 101, ptr %v6)
60  call void @llvm.lifetime.end(i64 100, ptr %v5)
61  call void @llvm.lifetime.end(i64 4, ptr %v4)
62  call void @llvm.lifetime.end(i64 4, ptr %v3)
63  call void @llvm.lifetime.end(i64 2, ptr %v2)
64  call void @llvm.lifetime.end(i64 1, ptr %v1)
65  ret void
66}
67
68declare void @llvm.lifetime.start(i64, ptr nocapture) #0
69declare void @llvm.lifetime.end(i64, ptr nocapture) #0
70declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1) #0
71
72declare void @test3(ptr, ptr, ptr, ptr, ptr, ptr)
73declare void @test4(ptr, ptr, ptr, ptr)
74
75attributes #0 = { argmemonly nounwind "target-cpu"="hexagonv60" }
76