1; RUN: llc -mtriple=hexagon < %s | FileCheck %s 2 3; This test checks to see if, after lowering the two loads below, we set up the 4; memrefs of the resulting load MIs correctly, so that they are packetized 5; together. 6 7; CHECK: { 8; CHECK: r{{[0-9]*}} = memw(r1{{[678]}}+#0) 9; CHECK-NEXT: r{{[0-9]*}} = memw(r1{{[678]}}+#0) 10 11; Function Attrs: nounwind 12define i64 @f0(ptr nocapture %a0, ptr nocapture %a1, ptr nocapture %a2) #0 { 13b0: 14 %v0 = tail call i32 @f1() #0 15 store i32 %v0, ptr %a2, align 4, !tbaa !0 16 %v1 = load i32, ptr %a0, align 4, !tbaa !0 17 %v2 = sext i32 %v1 to i64 18 %v3 = load i32, ptr %a1, align 4, !tbaa !0 19 %v4 = sext i32 %v3 to i64 20 %v5 = mul nsw i64 %v4, %v2 21 ret i64 %v5 22} 23 24declare i32 @f1(...) 25 26attributes #0 = { nounwind } 27 28!0 = !{!1, !1, i64 0} 29!1 = !{!"int", !2} 30!2 = !{!"omnipotent char", !3} 31!3 = !{!"Simple C/C++ TBAA"} 32