1; RUN: llc -mtriple=hexagon -mcpu=hexagonv68 -mattr=+hvxv68,+hvx-length128b < %s | FileCheck %s 2 3; Do not generate selectI1,Q,Q. 4; CHECK: q[[Q:[0-9]+]] = vsetq(r{{[0-9]+}}) 5; CHECK: q{{[0-9]+}} = and(q{{[0-9]+}},q[[Q]]) 6; CHECK-NOT: v{{[0-9]+}} = vand(q{{[0-9]+}},r{{[0-9]+}}) 7 8target triple = "hexagon" 9 10declare void @llvm.hexagon.V6.vS32b.qpred.ai.128B(<128 x i1>, ptr, <32 x i32>) #0 11declare <128 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32) #1 12declare <128 x i1> @llvm.hexagon.V6.pred.and.128B(<128 x i1>, <128 x i1>) #1 13 14define void @libjit_convertFromD32_sm_hf_wrap_3_specialized(ptr %0) local_unnamed_addr #2 { 15entry: 16 %arrayidx55.i.i = getelementptr inbounds i16, ptr %0, i32 undef 17 %1 = ptrtoint ptr %arrayidx55.i.i to i32 18 %and.i5.i.i = and i32 %1, 127 19 %2 = icmp eq i32 %and.i5.i.i, 127 20 %.sroa.speculated.i13.i.i = zext i1 %2 to i32 21 %3 = tail call <128 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32 %.sroa.speculated.i13.i.i) #3 22 %4 = tail call <128 x i1> @llvm.hexagon.V6.pred.and.128B(<128 x i1> undef, <128 x i1> %3) #3 23 tail call void @llvm.hexagon.V6.vS32b.qpred.ai.128B(<128 x i1> %4, ptr nonnull undef, <32 x i32> undef) #3 24 ret void 25} 26 27attributes #0 = { nounwind writeonly } 28attributes #1 = { nounwind readnone } 29attributes #2 = { "use-soft-float"="false" } 30attributes #3 = { nounwind } 31