xref: /llvm-project/llvm/test/CodeGen/Hexagon/prob-types.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956) 
1; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s
2; REQUIRES: asserts
3
4; This was aborting in Machine Loop Invariant Code Motion,
5; we want to see something generated in assembly.
6; CHECK: f0:
7
8target triple = "hexagon"
9
10; Function Attrs: nounwind readnone
11declare <32 x i32> @llvm.hexagon.V6.vdmpybus.128B(<32 x i32>, i32) #0
12
13; Function Attrs: nounwind readnone
14declare <32 x i32> @llvm.hexagon.V6.vlalignbi.128B(<32 x i32>, <32 x i32>, i32) #0
15
16; Function Attrs: nounwind readnone
17declare <32 x i32> @llvm.hexagon.V6.vaddh.128B(<32 x i32>, <32 x i32>) #0
18
19; Function Attrs: nounwind readnone
20declare <32 x i32> @llvm.hexagon.V6.vlalignb.128B(<32 x i32>, <32 x i32>, i32) #0
21
22; Function Attrs: nounwind readnone
23declare <32 x i32> @llvm.hexagon.V6.vand.128B(<32 x i32>, <32 x i32>) #0
24
25; Function Attrs: nounwind readnone
26declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #0
27
28; Function Attrs: nounwind readnone
29declare <32 x i32> @llvm.hexagon.V6.vrdelta.128B(<32 x i32>, <32 x i32>) #0
30
31; Function Attrs: nounwind readnone
32declare <64 x i32> @llvm.hexagon.V6.vunpackuh.128B(<32 x i32>) #0
33
34; Function Attrs: nounwind readnone
35declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #0
36
37; Function Attrs: nounwind readnone
38declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #0
39
40; Function Attrs: nounwind readnone
41declare <32 x i32> @llvm.hexagon.V6.vaddw.128B(<32 x i32>, <32 x i32>) #0
42
43; Function Attrs: nounwind
44define hidden void @f0(ptr %a0, ptr %a1, i32 %a2, <32 x i32> %a3, <32 x i32> %a4, <32 x i32> %a5, i32 %a6, <32 x i32> %a7) #1 {
45b0:
46  br label %b1
47
48b1:                                               ; preds = %b1, %b0
49  %v0 = phi ptr [ %v38, %b1 ], [ %a0, %b0 ]
50  %v1 = phi ptr [ %v4, %b1 ], [ %a1, %b0 ]
51  %v2 = phi i32 [ %v39, %b1 ], [ %a2, %b0 ]
52  %v3 = phi <32 x i32> [ %v34, %b1 ], [ %a3, %b0 ]
53  %v4 = getelementptr inbounds <32 x i32>, ptr %v1, i32 1
54  %v5 = load <32 x i32>, ptr %v1, align 128, !tbaa !0
55  %v6 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.128B(<32 x i32> %v5, i32 16843009) #2
56  %v7 = tail call <32 x i32> @llvm.hexagon.V6.vlalignbi.128B(<32 x i32> %v6, <32 x i32> %a4, i32 2) #2
57  %v8 = tail call <32 x i32> @llvm.hexagon.V6.vaddh.128B(<32 x i32> %v6, <32 x i32> %v7) #2
58  %v9 = tail call <32 x i32> @llvm.hexagon.V6.vlalignbi.128B(<32 x i32> %v8, <32 x i32> %a4, i32 4) #2
59  %v10 = tail call <32 x i32> @llvm.hexagon.V6.vaddh.128B(<32 x i32> %v8, <32 x i32> %v9) #2
60  %v11 = tail call <32 x i32> @llvm.hexagon.V6.vlalignb.128B(<32 x i32> %v10, <32 x i32> %a4, i32 8) #2
61  %v12 = tail call <32 x i32> @llvm.hexagon.V6.vaddh.128B(<32 x i32> %v10, <32 x i32> %v11) #2
62  %v13 = tail call <32 x i32> @llvm.hexagon.V6.vlalignb.128B(<32 x i32> %v12, <32 x i32> %a4, i32 16) #2
63  %v14 = tail call <32 x i32> @llvm.hexagon.V6.vaddh.128B(<32 x i32> %v12, <32 x i32> %v13) #2
64  %v15 = tail call <32 x i32> @llvm.hexagon.V6.vlalignb.128B(<32 x i32> %v14, <32 x i32> %a4, i32 32) #2
65  %v16 = tail call <32 x i32> @llvm.hexagon.V6.vaddh.128B(<32 x i32> %v14, <32 x i32> %v15) #2
66  %v17 = tail call <32 x i32> @llvm.hexagon.V6.vaddh.128B(<32 x i32> %v16, <32 x i32> %v15) #2
67  %v18 = tail call <32 x i32> @llvm.hexagon.V6.vand.128B(<32 x i32> %v5, <32 x i32> %a5) #2
68  %v19 = tail call <32 x i32> @llvm.hexagon.V6.vlalignbi.128B(<32 x i32> %v17, <32 x i32> %a4, i32 2) #2
69  %v20 = tail call <32 x i32> @llvm.hexagon.V6.vaddh.128B(<32 x i32> %v19, <32 x i32> %v18) #2
70  %v21 = tail call <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32> %v17, <32 x i32> %v20, i32 -2) #2
71  %v22 = tail call <32 x i32> @llvm.hexagon.V6.vrdelta.128B(<32 x i32> %v3, <32 x i32> %a7) #2
72  %v23 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v21) #2
73  %v24 = tail call <64 x i32> @llvm.hexagon.V6.vunpackuh.128B(<32 x i32> %v23) #2
74  %v25 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v21) #2
75  %v26 = tail call <64 x i32> @llvm.hexagon.V6.vunpackuh.128B(<32 x i32> %v25) #2
76  %v27 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v24) #2
77  %v28 = tail call <32 x i32> @llvm.hexagon.V6.vaddw.128B(<32 x i32> %v22, <32 x i32> %v27) #2
78  %v29 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v24) #2
79  %v30 = tail call <32 x i32> @llvm.hexagon.V6.vaddw.128B(<32 x i32> %v22, <32 x i32> %v29) #2
80  %v31 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v26) #2
81  %v32 = tail call <32 x i32> @llvm.hexagon.V6.vaddw.128B(<32 x i32> %v22, <32 x i32> %v31) #2
82  %v33 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v26) #2
83  %v34 = tail call <32 x i32> @llvm.hexagon.V6.vaddw.128B(<32 x i32> %v22, <32 x i32> %v33) #2
84  %v35 = getelementptr inbounds <32 x i32>, ptr %v0, i32 1
85  store <32 x i32> %v28, ptr %v0, align 128, !tbaa !0
86  %v36 = getelementptr inbounds <32 x i32>, ptr %v0, i32 2
87  store <32 x i32> %v30, ptr %v35, align 128, !tbaa !0
88  %v37 = getelementptr inbounds <32 x i32>, ptr %v0, i32 3
89  store <32 x i32> %v32, ptr %v36, align 128, !tbaa !0
90  %v38 = getelementptr inbounds <32 x i32>, ptr %v0, i32 4
91  store <32 x i32> %v34, ptr %v37, align 128, !tbaa !0
92  %v39 = add nsw i32 %v2, 128
93  %v40 = icmp slt i32 %v39, %a6
94  br i1 %v40, label %b1, label %b2
95
96b2:                                               ; preds = %b1
97  ret void
98}
99
100attributes #0 = { nounwind readnone }
101attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
102attributes #2 = { nounwind }
103
104!0 = !{!1, !1, i64 0}
105!1 = !{!"omnipotent char", !2, i64 0}
106!2 = !{!"Simple C/C++ TBAA"}
107