xref: /llvm-project/llvm/test/CodeGen/Hexagon/mpy.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956)
1; RUN: llc -mtriple=hexagon < %s | FileCheck %s
2; CHECK: += mpyi
3
4define void @f0(i32 %a0, i32 %a1, i32 %a2) #0 {
5b0:
6  %v0 = alloca i32, align 4
7  %v1 = alloca i32, align 4
8  %v2 = alloca i32, align 4
9  store i32 %a0, ptr %v0, align 4
10  store i32 %a1, ptr %v1, align 4
11  store i32 %a2, ptr %v2, align 4
12  %v3 = load i32, ptr %v1, align 4
13  %v4 = load i32, ptr %v0, align 4
14  %v5 = mul nsw i32 %v3, %v4
15  %v6 = load i32, ptr %v2, align 4
16  %v7 = add nsw i32 %v5, %v6
17  store i32 %v7, ptr %v1, align 4
18  ret void
19}
20
21attributes #0 = { nounwind "target-cpu"="hexagonv5" }
22