xref: /llvm-project/llvm/test/CodeGen/Hexagon/isel/select-i1.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc -mtriple=hexagon < %s | FileCheck %s
3
4define void @f0(ptr %a0, ptr %a1, ptr %a2, ptr %a3) {
5; CHECK-LABEL: f0:
6; CHECK:         .cfi_startproc
7; CHECK-NEXT:  // %bb.0: // %b0
8; CHECK-NEXT:    {
9; CHECK-NEXT:     r0 = memub(r0+#0)
10; CHECK-NEXT:    }
11; CHECK-NEXT:    {
12; CHECK-NEXT:     p0 = r0
13; CHECK-NEXT:    }
14; CHECK-NEXT:    {
15; CHECK-NEXT:     r0 = mux(p0,r1,r2)
16; CHECK-NEXT:    }
17; CHECK-NEXT:    {
18; CHECK-NEXT:     r0 = memub(r0+#0)
19; CHECK-NEXT:    }
20; CHECK-NEXT:    {
21; CHECK-NEXT:     p0 = r0
22; CHECK-NEXT:    }
23; CHECK-NEXT:    {
24; CHECK-NEXT:     r0 = mux(p0,#1,#0)
25; CHECK-NEXT:     jumpr r31
26; CHECK-NEXT:     memb(r3+#0) = r0.new
27; CHECK-NEXT:    }
28b0:
29  %v0 = load i1, ptr %a0
30  %v1 = load i1, ptr %a1
31  %v2 = load i1, ptr %a2
32  %v3 = select i1 %v0, i1 %v1, i1 %v2
33  store i1 %v3, ptr %a3
34  ret void
35}
36
37define void @f1(ptr %a0, ptr %a1, ptr %a2, ptr %a3) {
38; CHECK-LABEL: f1:
39; CHECK:         .cfi_startproc
40; CHECK-NEXT:  // %bb.0: // %b0
41; CHECK-NEXT:    {
42; CHECK-NEXT:     r0 = memub(r0+#0)
43; CHECK-NEXT:    }
44; CHECK-NEXT:    {
45; CHECK-NEXT:     p0 = r0
46; CHECK-NEXT:    }
47; CHECK-NEXT:    {
48; CHECK-NEXT:     r0 = mux(p0,r1,r2)
49; CHECK-NEXT:    }
50; CHECK-NEXT:    {
51; CHECK-NEXT:     jumpr r31
52; CHECK-NEXT:     r0 = memub(r0+#0)
53; CHECK-NEXT:     memb(r3+#0) = r0.new
54; CHECK-NEXT:    }
55b0:
56  %v0 = load i1, ptr %a0
57  %v1 = load <2 x i1>, ptr %a1
58  %v2 = load <2 x i1>, ptr %a2
59  %v3 = select i1 %v0, <2 x i1> %v1, <2 x i1> %v2
60  store <2 x i1> %v3, ptr %a3
61  ret void
62}
63
64define void @f2(ptr %a0, ptr %a1, ptr %a2, ptr %a3) {
65; CHECK-LABEL: f2:
66; CHECK:         .cfi_startproc
67; CHECK-NEXT:  // %bb.0: // %b0
68; CHECK-NEXT:    {
69; CHECK-NEXT:     r0 = memub(r0+#0)
70; CHECK-NEXT:    }
71; CHECK-NEXT:    {
72; CHECK-NEXT:     p0 = r0
73; CHECK-NEXT:    }
74; CHECK-NEXT:    {
75; CHECK-NEXT:     r0 = mux(p0,r1,r2)
76; CHECK-NEXT:    }
77; CHECK-NEXT:    {
78; CHECK-NEXT:     jumpr r31
79; CHECK-NEXT:     r0 = memub(r0+#0)
80; CHECK-NEXT:     memb(r3+#0) = r0.new
81; CHECK-NEXT:    }
82b0:
83  %v0 = load i1, ptr %a0
84  %v1 = load <4 x i1>, ptr %a1
85  %v2 = load <4 x i1>, ptr %a2
86  %v3 = select i1 %v0, <4 x i1> %v1, <4 x i1> %v2
87  store <4 x i1> %v3, ptr %a3
88  ret void
89}
90
91define void @f3(ptr %a0, ptr %a1, ptr %a2, ptr %a3) {
92; CHECK-LABEL: f3:
93; CHECK:         .cfi_startproc
94; CHECK-NEXT:  // %bb.0: // %b0
95; CHECK-NEXT:    {
96; CHECK-NEXT:     r0 = memub(r0+#0)
97; CHECK-NEXT:    }
98; CHECK-NEXT:    {
99; CHECK-NEXT:     p0 = r0
100; CHECK-NEXT:    }
101; CHECK-NEXT:    {
102; CHECK-NEXT:     r0 = mux(p0,r1,r2)
103; CHECK-NEXT:    }
104; CHECK-NEXT:    {
105; CHECK-NEXT:     jumpr r31
106; CHECK-NEXT:     r0 = memub(r0+#0)
107; CHECK-NEXT:     memb(r3+#0) = r0.new
108; CHECK-NEXT:    }
109b0:
110  %v0 = load i1, ptr %a0
111  %v1 = load <8 x i1>, ptr %a1
112  %v2 = load <8 x i1>, ptr %a2
113  %v3 = select i1 %v0, <8 x i1> %v1, <8 x i1> %v2
114  store <8 x i1> %v3, ptr %a3
115  ret void
116}
117
118define void @f4(ptr %a0, ptr %a1, ptr %a2, ptr %a3) {
119; CHECK-LABEL: f4:
120; CHECK:         .cfi_startproc
121; CHECK-NEXT:  // %bb.0: // %b0
122; CHECK-NEXT:    {
123; CHECK-NEXT:     r1 = memub(r1+#0)
124; CHECK-NEXT:     r0 = memub(r0+#0)
125; CHECK-NEXT:    }
126; CHECK-NEXT:    {
127; CHECK-NEXT:     r2 = memub(r2+#0)
128; CHECK-NEXT:    }
129; CHECK-NEXT:    {
130; CHECK-NEXT:     p0 = r0
131; CHECK-NEXT:     p1 = r1
132; CHECK-NEXT:    }
133; CHECK-NEXT:    {
134; CHECK-NEXT:     p2 = r2
135; CHECK-NEXT:     p1 = and(p1,p0)
136; CHECK-NEXT:    }
137; CHECK-NEXT:    {
138; CHECK-NEXT:     p0 = or(p1,and(p2,!p0))
139; CHECK-NEXT:    }
140; CHECK-NEXT:    {
141; CHECK-NEXT:     r2 = p0
142; CHECK-NEXT:     jumpr r31
143; CHECK-NEXT:     memb(r3+#0) = r2.new
144; CHECK-NEXT:    }
145b0:
146  %v0 = load <2 x i1>, ptr %a0
147  %v1 = load <2 x i1>, ptr %a1
148  %v2 = load <2 x i1>, ptr %a2
149  %v3 = select <2 x i1> %v0, <2 x i1> %v1, <2 x i1> %v2
150  store <2 x i1> %v3, ptr %a3
151  ret void
152}
153
154define void @f5(ptr %a0, ptr %a1, ptr %a2, ptr %a3) {
155; CHECK-LABEL: f5:
156; CHECK:         .cfi_startproc
157; CHECK-NEXT:  // %bb.0: // %b0
158; CHECK-NEXT:    {
159; CHECK-NEXT:     r1 = memub(r1+#0)
160; CHECK-NEXT:     r0 = memub(r0+#0)
161; CHECK-NEXT:    }
162; CHECK-NEXT:    {
163; CHECK-NEXT:     r2 = memub(r2+#0)
164; CHECK-NEXT:    }
165; CHECK-NEXT:    {
166; CHECK-NEXT:     p0 = r0
167; CHECK-NEXT:     p1 = r1
168; CHECK-NEXT:    }
169; CHECK-NEXT:    {
170; CHECK-NEXT:     p2 = r2
171; CHECK-NEXT:     p1 = and(p1,p0)
172; CHECK-NEXT:    }
173; CHECK-NEXT:    {
174; CHECK-NEXT:     p0 = or(p1,and(p2,!p0))
175; CHECK-NEXT:    }
176; CHECK-NEXT:    {
177; CHECK-NEXT:     r2 = p0
178; CHECK-NEXT:     jumpr r31
179; CHECK-NEXT:     memb(r3+#0) = r2.new
180; CHECK-NEXT:    }
181b0:
182  %v0 = load <4 x i1>, ptr %a0
183  %v1 = load <4 x i1>, ptr %a1
184  %v2 = load <4 x i1>, ptr %a2
185  %v3 = select <4 x i1> %v0, <4 x i1> %v1, <4 x i1> %v2
186  store <4 x i1> %v3, ptr %a3
187  ret void
188}
189
190define void @f6(ptr %a0, ptr %a1, ptr %a2, ptr %a3) {
191; CHECK-LABEL: f6:
192; CHECK:         .cfi_startproc
193; CHECK-NEXT:  // %bb.0: // %b0
194; CHECK-NEXT:    {
195; CHECK-NEXT:     r1 = memub(r1+#0)
196; CHECK-NEXT:     r0 = memub(r0+#0)
197; CHECK-NEXT:    }
198; CHECK-NEXT:    {
199; CHECK-NEXT:     r2 = memub(r2+#0)
200; CHECK-NEXT:    }
201; CHECK-NEXT:    {
202; CHECK-NEXT:     p0 = r0
203; CHECK-NEXT:     p1 = r1
204; CHECK-NEXT:    }
205; CHECK-NEXT:    {
206; CHECK-NEXT:     p2 = r2
207; CHECK-NEXT:     p1 = and(p1,p0)
208; CHECK-NEXT:    }
209; CHECK-NEXT:    {
210; CHECK-NEXT:     p0 = or(p1,and(p2,!p0))
211; CHECK-NEXT:    }
212; CHECK-NEXT:    {
213; CHECK-NEXT:     r2 = p0
214; CHECK-NEXT:     jumpr r31
215; CHECK-NEXT:     memb(r3+#0) = r2.new
216; CHECK-NEXT:    }
217b0:
218  %v0 = load <8 x i1>, ptr %a0
219  %v1 = load <8 x i1>, ptr %a1
220  %v2 = load <8 x i1>, ptr %a2
221  %v3 = select <8 x i1> %v0, <8 x i1> %v1, <8 x i1> %v2
222  store <8 x i1> %v3, ptr %a3
223  ret void
224}
225