xref: /llvm-project/llvm/test/CodeGen/Hexagon/isel/extload-i1.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=hexagon < %s | FileCheck %s
3
4@array8 = global [128 x i8] zeroinitializer
5@array32 = global [128 x i32] zeroinitializer
6@global_gp = global i1 false
7
8; Sign extensions
9
10define i32 @f0(ptr %a0) #0 {
11; CHECK-LABEL: f0:
12; CHECK:       // %bb.0:
13; CHECK-NEXT:    {
14; CHECK-NEXT:     r0 = memub(r0+#1)
15; CHECK-NEXT:    }
16; CHECK-NEXT:    {
17; CHECK-NEXT:     r0 = sub(#0,r0)
18; CHECK-NEXT:     jumpr r31
19; CHECK-NEXT:    }
20  %v0 = getelementptr i1, ptr %a0, i32 1
21  %v1 = load i1, ptr %v0
22  %v2 = sext i1 %v1 to i32
23  ret i32 %v2
24}
25
26define i32 @f1(ptr %a0, i32 %a1) #0 {
27; CHECK-LABEL: f1:
28; CHECK:       // %bb.0:
29; CHECK-NEXT:    {
30; CHECK-NEXT:     r0 = memub(r0+r1<<#0)
31; CHECK-NEXT:    }
32; CHECK-NEXT:    {
33; CHECK-NEXT:     r0 = sub(#0,r0)
34; CHECK-NEXT:     jumpr r31
35; CHECK-NEXT:    }
36  %v0 = getelementptr i1, ptr %a0, i32 %a1
37  %v1 = load i1, ptr %v0
38  %v2 = sext i1 %v1 to i32
39  ret i32 %v2
40}
41
42define i32 @f2(i32 %a0) #0 {
43; CHECK-LABEL: f2:
44; CHECK:       // %bb.0:
45; CHECK-NEXT:    {
46; CHECK-NEXT:     r0 = memub(r0+##array8)
47; CHECK-NEXT:    }
48; CHECK-NEXT:    {
49; CHECK-NEXT:     r0 = sub(#0,r0)
50; CHECK-NEXT:     jumpr r31
51; CHECK-NEXT:    }
52  %v0 = getelementptr [128 x i8], ptr @array8, i32 0, i32 %a0
53  %v2 = load i1, ptr %v0
54  %v3 = sext i1 %v2 to i32
55  ret i32 %v3
56}
57
58define i32 @f3(i32 %a0) #0 {
59; CHECK-LABEL: f3:
60; CHECK:       // %bb.0:
61; CHECK-NEXT:    {
62; CHECK-NEXT:     r0 = memub(r0<<#2+##array32)
63; CHECK-NEXT:    }
64; CHECK-NEXT:    {
65; CHECK-NEXT:     r0 = sub(#0,r0)
66; CHECK-NEXT:     jumpr r31
67; CHECK-NEXT:    }
68  %v0 = getelementptr [128 x i32], ptr @array32, i32 0, i32 %a0
69  %v2 = load i1, ptr %v0
70  %v3 = sext i1 %v2 to i32
71  ret i32 %v3
72}
73
74define i32 @f4() #0 {
75; CHECK-LABEL: f4:
76; CHECK:       // %bb.0:
77; CHECK-NEXT:    {
78; CHECK-NEXT:     r0 = memub(gp+#global_gp)
79; CHECK-NEXT:    }
80; CHECK-NEXT:    {
81; CHECK-NEXT:     r0 = sub(#0,r0)
82; CHECK-NEXT:     jumpr r31
83; CHECK-NEXT:    }
84  %v0 = load i1, ptr @global_gp
85  %v1 = sext i1 %v0 to i32
86  ret i32 %v1
87}
88
89define i32 @f5(i64 %a0, i64 %a1, i64 %a2, i1 signext %a3) #0 {
90; CHECK-LABEL: f5:
91; CHECK:       // %bb.0:
92; CHECK-NEXT:    {
93; CHECK-NEXT:     r0 = memub(r29+#0)
94; CHECK-NEXT:    }
95; CHECK-NEXT:    {
96; CHECK-NEXT:     r0 = sub(#0,r0)
97; CHECK-NEXT:     jumpr r31
98; CHECK-NEXT:    }
99  %v0 = sext i1 %a3 to i32
100  ret i32 %v0
101}
102
103define i64 @f6(ptr %a0) #0 {
104; CHECK-LABEL: f6:
105; CHECK:       // %bb.0:
106; CHECK-NEXT:    {
107; CHECK-NEXT:     r0 = memub(r0+#1)
108; CHECK-NEXT:    }
109; CHECK-NEXT:    {
110; CHECK-NEXT:     r0 = sub(#0,r0)
111; CHECK-NEXT:    }
112; CHECK-NEXT:    {
113; CHECK-NEXT:     r1 = asr(r0,#31)
114; CHECK-NEXT:     jumpr r31
115; CHECK-NEXT:    }
116  %v0 = getelementptr i1, ptr %a0, i32 1
117  %v1 = load i1, ptr %v0
118  %v2 = sext i1 %v1 to i64
119  ret i64 %v2
120}
121
122define i64 @f7(ptr %a0, i32 %a1) #0 {
123; CHECK-LABEL: f7:
124; CHECK:       // %bb.0:
125; CHECK-NEXT:    {
126; CHECK-NEXT:     r0 = memub(r0+r1<<#0)
127; CHECK-NEXT:    }
128; CHECK-NEXT:    {
129; CHECK-NEXT:     r0 = sub(#0,r0)
130; CHECK-NEXT:    }
131; CHECK-NEXT:    {
132; CHECK-NEXT:     r1 = asr(r0,#31)
133; CHECK-NEXT:     jumpr r31
134; CHECK-NEXT:    }
135  %v0 = getelementptr i1, ptr %a0, i32 %a1
136  %v1 = load i1, ptr %v0
137  %v2 = sext i1 %v1 to i64
138  ret i64 %v2
139}
140
141define i64 @f8(i32 %a0) #0 {
142; CHECK-LABEL: f8:
143; CHECK:       // %bb.0:
144; CHECK-NEXT:    {
145; CHECK-NEXT:     r0 = memub(r0+##array8)
146; CHECK-NEXT:    }
147; CHECK-NEXT:    {
148; CHECK-NEXT:     r0 = sub(#0,r0)
149; CHECK-NEXT:    }
150; CHECK-NEXT:    {
151; CHECK-NEXT:     r1 = asr(r0,#31)
152; CHECK-NEXT:     jumpr r31
153; CHECK-NEXT:    }
154  %v0 = getelementptr [128 x i8], ptr @array8, i32 0, i32 %a0
155  %v2 = load i1, ptr %v0
156  %v3 = sext i1 %v2 to i64
157  ret i64 %v3
158}
159
160define i64 @f9(i32 %a0) #0 {
161; CHECK-LABEL: f9:
162; CHECK:       // %bb.0:
163; CHECK-NEXT:    {
164; CHECK-NEXT:     r0 = memub(r0<<#2+##array32)
165; CHECK-NEXT:    }
166; CHECK-NEXT:    {
167; CHECK-NEXT:     r0 = sub(#0,r0)
168; CHECK-NEXT:    }
169; CHECK-NEXT:    {
170; CHECK-NEXT:     r1 = asr(r0,#31)
171; CHECK-NEXT:     jumpr r31
172; CHECK-NEXT:    }
173  %v0 = getelementptr [128 x i32], ptr @array32, i32 0, i32 %a0
174  %v2 = load i1, ptr %v0
175  %v3 = sext i1 %v2 to i64
176  ret i64 %v3
177}
178
179define i64 @f10() #0 {
180; CHECK-LABEL: f10:
181; CHECK:       // %bb.0:
182; CHECK-NEXT:    {
183; CHECK-NEXT:     r0 = memub(gp+#global_gp)
184; CHECK-NEXT:    }
185; CHECK-NEXT:    {
186; CHECK-NEXT:     r0 = sub(#0,r0)
187; CHECK-NEXT:    }
188; CHECK-NEXT:    {
189; CHECK-NEXT:     r1 = asr(r0,#31)
190; CHECK-NEXT:     jumpr r31
191; CHECK-NEXT:    }
192  %v0 = load i1, ptr @global_gp
193  %v1 = sext i1 %v0 to i64
194  ret i64 %v1
195}
196
197define i64 @f11(i64 %a0, i64 %a1, i64 %a2, i1 signext %a3) #0 {
198; CHECK-LABEL: f11:
199; CHECK:       // %bb.0:
200; CHECK-NEXT:    {
201; CHECK-NEXT:     r0 = memub(r29+#0)
202; CHECK-NEXT:    }
203; CHECK-NEXT:    {
204; CHECK-NEXT:     r0 = sub(#0,r0)
205; CHECK-NEXT:    }
206; CHECK-NEXT:    {
207; CHECK-NEXT:     r1 = asr(r0,#31)
208; CHECK-NEXT:     jumpr r31
209; CHECK-NEXT:    }
210  %v0 = sext i1 %a3 to i64
211  ret i64 %v0
212}
213
214; Zero-extensions
215
216define i32 @f12(ptr %a0) #0 {
217; CHECK-LABEL: f12:
218; CHECK:       // %bb.0:
219; CHECK-NEXT:    {
220; CHECK-NEXT:     r0 = memub(r0+#1)
221; CHECK-NEXT:     jumpr r31
222; CHECK-NEXT:    }
223  %v0 = getelementptr i1, ptr %a0, i32 1
224  %v1 = load i1, ptr %v0
225  %v2 = zext i1 %v1 to i32
226  ret i32 %v2
227}
228
229define i32 @f13(ptr %a0, i32 %a1) #0 {
230; CHECK-LABEL: f13:
231; CHECK:       // %bb.0:
232; CHECK-NEXT:    {
233; CHECK-NEXT:     jumpr r31
234; CHECK-NEXT:     r0 = memub(r0+r1<<#0)
235; CHECK-NEXT:    }
236  %v0 = getelementptr i1, ptr %a0, i32 %a1
237  %v1 = load i1, ptr %v0
238  %v2 = zext i1 %v1 to i32
239  ret i32 %v2
240}
241
242define i32 @f14(i32 %a0) #0 {
243; CHECK-LABEL: f14:
244; CHECK:       // %bb.0:
245; CHECK-NEXT:    {
246; CHECK-NEXT:     jumpr r31
247; CHECK-NEXT:     r0 = memub(r0+##array8)
248; CHECK-NEXT:    }
249  %v0 = getelementptr [128 x i8], ptr @array8, i32 0, i32 %a0
250  %v2 = load i1, ptr %v0
251  %v3 = zext i1 %v2 to i32
252  ret i32 %v3
253}
254
255define i32 @f15(i32 %a0) #0 {
256; CHECK-LABEL: f15:
257; CHECK:       // %bb.0:
258; CHECK-NEXT:    {
259; CHECK-NEXT:     jumpr r31
260; CHECK-NEXT:     r0 = memub(r0<<#2+##array32)
261; CHECK-NEXT:    }
262  %v0 = getelementptr [128 x i32], ptr @array32, i32 0, i32 %a0
263  %v2 = load i1, ptr %v0
264  %v3 = zext i1 %v2 to i32
265  ret i32 %v3
266}
267
268define i32 @f16() #0 {
269; CHECK-LABEL: f16:
270; CHECK:       // %bb.0:
271; CHECK-NEXT:    {
272; CHECK-NEXT:     jumpr r31
273; CHECK-NEXT:     r0 = memub(gp+#global_gp)
274; CHECK-NEXT:    }
275  %v0 = load i1, ptr @global_gp
276  %v1 = zext i1 %v0 to i32
277  ret i32 %v1
278}
279
280define i32 @f17(i64 %a0, i64 %a1, i64 %a2, i1 zeroext %a3) #0 {
281; CHECK-LABEL: f17:
282; CHECK:       // %bb.0:
283; CHECK-NEXT:    {
284; CHECK-NEXT:     jumpr r31
285; CHECK-NEXT:     r0 = memub(r29+#0)
286; CHECK-NEXT:    }
287  %v0 = zext i1 %a3 to i32
288  ret i32 %v0
289}
290
291define i64 @f18(ptr %a0) #0 {
292; CHECK-LABEL: f18:
293; CHECK:       // %bb.0:
294; CHECK-NEXT:    {
295; CHECK-NEXT:     jumpr r31
296; CHECK-NEXT:     r1 = #0
297; CHECK-NEXT:     r0 = memub(r0+#1)
298; CHECK-NEXT:    }
299  %v0 = getelementptr i1, ptr %a0, i32 1
300  %v1 = load i1, ptr %v0
301  %v2 = zext i1 %v1 to i64
302  ret i64 %v2
303}
304
305define i64 @f19(ptr %a0, i32 %a1) #0 {
306; CHECK-LABEL: f19:
307; CHECK:       // %bb.0:
308; CHECK-NEXT:    {
309; CHECK-NEXT:     r1 = #0
310; CHECK-NEXT:     jumpr r31
311; CHECK-NEXT:     r0 = memub(r0+r1<<#0)
312; CHECK-NEXT:    }
313  %v0 = getelementptr i1, ptr %a0, i32 %a1
314  %v1 = load i1, ptr %v0
315  %v2 = zext i1 %v1 to i64
316  ret i64 %v2
317}
318
319define i64 @f20(i32 %a0) #0 {
320; CHECK-LABEL: f20:
321; CHECK:       // %bb.0:
322; CHECK-NEXT:    {
323; CHECK-NEXT:     r1 = #0
324; CHECK-NEXT:     jumpr r31
325; CHECK-NEXT:     r0 = memub(r0+##array8)
326; CHECK-NEXT:    }
327  %v0 = getelementptr [128 x i8], ptr @array8, i32 0, i32 %a0
328  %v2 = load i1, ptr %v0
329  %v3 = zext i1 %v2 to i64
330  ret i64 %v3
331}
332
333define i64 @f21(i32 %a0) #0 {
334; CHECK-LABEL: f21:
335; CHECK:       // %bb.0:
336; CHECK-NEXT:    {
337; CHECK-NEXT:     r1 = #0
338; CHECK-NEXT:     jumpr r31
339; CHECK-NEXT:     r0 = memub(r0<<#2+##array32)
340; CHECK-NEXT:    }
341  %v0 = getelementptr [128 x i32], ptr @array32, i32 0, i32 %a0
342  %v2 = load i1, ptr %v0
343  %v3 = zext i1 %v2 to i64
344  ret i64 %v3
345}
346
347define i64 @f22() #0 {
348; CHECK-LABEL: f22:
349; CHECK:       // %bb.0:
350; CHECK-NEXT:    {
351; CHECK-NEXT:     r1 = #0
352; CHECK-NEXT:     jumpr r31
353; CHECK-NEXT:     r0 = memub(gp+#global_gp)
354; CHECK-NEXT:    }
355  %v0 = load i1, ptr @global_gp
356  %v1 = zext i1 %v0 to i64
357  ret i64 %v1
358}
359
360define i64 @f23(i64 %a0, i64 %a1, i64 %a2, i1 signext %a3) #0 {
361; CHECK-LABEL: f23:
362; CHECK:       // %bb.0:
363; CHECK-NEXT:    {
364; CHECK-NEXT:     r1 = #0
365; CHECK-NEXT:     jumpr r31
366; CHECK-NEXT:     r0 = memub(r29+#0)
367; CHECK-NEXT:    }
368  %v0 = zext i1 %a3 to i64
369  ret i64 %v0
370}
371
372attributes #0 = { nounwind "target-cpu"="hexagonv66" }
373