xref: /llvm-project/llvm/test/CodeGen/Hexagon/isel-fold-shl-zext.ll (revision f7d354af5714358d7ad83e58a1016c3f385416dd)
1; RUN: llc -mtriple=hexagon-unknown-elf < %s | FileCheck %s
2
3; In ISelLowering, when folding nodes (or (shl xx, s), (zext y))
4; to (COMBINE (shl xx, s-32), y) where s >= 32,
5; check that resulting shift value does not create an undef
6
7
8target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
9target triple = "hexagon"
10
11; Function Attrs: nofree nosync nounwind memory(readwrite, inaccessiblemem: none)
12define dso_local void @foo(i64* nocapture noundef %buf, i32 %a, i32 %b) local_unnamed_addr {
13; CHECK-LABEL: foo:
14; CHECK:       // %bb.0: // %entry
15; CHECK-NEXT:    {
16; CHECK-NEXT:     r[[REG0:[0-9]+]] = addasl(r2,r1,#1)
17; CHECK-NEXT:     r[[REG2:[0-9]+]] = asl(r1,#1)
18; CHECK-NEXT:    }
19; CHECK-NEXT:    {
20; CHECK-NEXT:     r[[REG1:[0-9]+]] = addasl(r[[REG0]],r1,#1)
21; CHECK-NEXT:    }
22; CHECK-NEXT:    {
23; CHECK-NEXT:     jumpr r31
24; CHECK-NEXT:     memd(r0+#8) = r[[REG2]]:[[REG1]]
25; CHECK-NEXT:    }
26entry:
27  %arrayidx = getelementptr inbounds i64, i64* %buf, i32 1
28  %add0 = shl nsw i32 %a, 1
29  %add1 = add nsw i32 %add0, %b
30  %add2 = add nsw i32 %add1, %add0
31  %ext0 = zext i32 %add0 to i64
32  %shift0 = shl nuw i64 %ext0, 32
33  %ext1 = zext i32 %add2 to i64
34  %or0 = or i64 %shift0, %ext1
35  store i64 %or0, i64* %arrayidx, align 8
36  ret void
37}
38