1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=hexagon < %s | FileCheck %s 3 4define i32 @f0(ptr %a0, i32 %a1) #0 { 5; CHECK-LABEL: f0: 6; CHECK: // %bb.0: 7; CHECK-NEXT: { 8; CHECK-NEXT: r0 = memub(r0+#0) 9; CHECK-NEXT: } 10; CHECK-NEXT: { 11; CHECK-NEXT: r1 = asl(r1,#2) 12; CHECK-NEXT: } 13; CHECK-NEXT: { 14; CHECK-NEXT: p0 = tstbit(r0,r1) 15; CHECK-NEXT: } 16; CHECK-NEXT: { 17; CHECK-NEXT: r0 = mux(p0,#-1,#0) 18; CHECK-NEXT: } 19; CHECK-NEXT: { 20; CHECK-NEXT: jumpr r31 21; CHECK-NEXT: } 22 %v0 = load <2 x i1>, ptr %a0 23 %v1 = extractelement <2 x i1> %v0, i32 %a1 24 %v2 = sext i1 %v1 to i32 25 ret i32 %v2 26} 27 28define i32 @f1(ptr %a0, i32 %a1) #0 { 29; CHECK-LABEL: f1: 30; CHECK: // %bb.0: 31; CHECK-NEXT: { 32; CHECK-NEXT: r0 = memub(r0+#0) 33; CHECK-NEXT: } 34; CHECK-NEXT: { 35; CHECK-NEXT: r1 = asl(r1,#1) 36; CHECK-NEXT: } 37; CHECK-NEXT: { 38; CHECK-NEXT: p0 = tstbit(r0,r1) 39; CHECK-NEXT: } 40; CHECK-NEXT: { 41; CHECK-NEXT: r0 = mux(p0,#-1,#0) 42; CHECK-NEXT: } 43; CHECK-NEXT: { 44; CHECK-NEXT: jumpr r31 45; CHECK-NEXT: } 46 %v0 = load <4 x i1>, ptr %a0 47 %v1 = extractelement <4 x i1> %v0, i32 %a1 48 %v2 = sext i1 %v1 to i32 49 ret i32 %v2 50} 51 52define i32 @f2(ptr %a0, i32 %a1) #0 { 53; CHECK-LABEL: f2: 54; CHECK: // %bb.0: 55; CHECK-NEXT: { 56; CHECK-NEXT: r0 = memub(r0+#0) 57; CHECK-NEXT: } 58; CHECK-NEXT: { 59; CHECK-NEXT: p0 = tstbit(r0,r1) 60; CHECK-NEXT: } 61; CHECK-NEXT: { 62; CHECK-NEXT: r0 = mux(p0,#-1,#0) 63; CHECK-NEXT: } 64; CHECK-NEXT: { 65; CHECK-NEXT: jumpr r31 66; CHECK-NEXT: } 67 %v0 = load <8 x i1>, ptr %a0 68 %v1 = extractelement <8 x i1> %v0, i32 %a1 69 %v2 = sext i1 %v1 to i32 70 ret i32 %v2 71} 72 73attributes #0 = { nounwind "target-features"="-packets" } 74