xref: /llvm-project/llvm/test/CodeGen/Hexagon/isel-extload-i1.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=hexagon < %s | FileCheck %s
3; RUN: llc -mtriple=hexagon -early-live-intervals -verify-machineinstrs < %s | FileCheck %s
4
5target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
6target triple = "hexagon"
7
8define i64 @f0(i32 %a0, i64 %a1, i32 %a2, i32 %a3, i1 zeroext %a4) #0 {
9; CHECK-LABEL: f0:
10; CHECK:       // %bb.0: // %b0
11; CHECK-NEXT:    {
12; CHECK-NEXT:     r0 = memub(r29+#0)
13; CHECK-NEXT:    }
14; CHECK-NEXT:    {
15; CHECK-NEXT:     r0 = sub(#0,r0)
16; CHECK-NEXT:    }
17; CHECK-NEXT:    {
18; CHECK-NEXT:     r1 = asr(r0,#31)
19; CHECK-NEXT:     jumpr r31
20; CHECK-NEXT:    }
21b0:
22  %v0 = sext i1 %a4 to i64
23  ret i64 %v0
24}
25
26attributes #0 = { nounwind "target-cpu"="hexagonv66" "target-features"="+v66,-long-calls" }
27