xref: /llvm-project/llvm/test/CodeGen/Hexagon/hwloop-subreg.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956)
1; RUN: llc -mtriple=hexagon < %s
2; REQUIRES: asserts
3
4target triple = "hexagon"
5
6; Function Attrs: nounwind optsize readonly
7define void @f0() #0 align 2 {
8b0:
9  %v0 = load i32, ptr undef, align 8
10  %v1 = zext i32 %v0 to i64
11  %v2 = add nuw nsw i64 %v1, 63
12  %v3 = lshr i64 %v2, 6
13  %v4 = trunc i64 %v3 to i32
14  br i1 undef, label %b3, label %b1
15
16b1:                                               ; preds = %b0
17  %v5 = add nsw i32 %v4, -1
18  br label %b2
19
20b2:                                               ; preds = %b2, %b1
21  %v6 = phi i32 [ %v5, %b1 ], [ %v7, %b2 ]
22  %v7 = add i32 %v6, -1
23  %v8 = icmp sgt i32 %v7, -1
24  br i1 %v8, label %b2, label %b3
25
26b3:                                               ; preds = %b2, %b0
27  ret void
28}
29
30attributes #0 = { nounwind optsize readonly }
31