1; RUN: llc -O2 -mtriple=hexagon -fp-contract=fast -pipeliner-prune-loop-carried=false < %s | FileCheck %s 2 3; Test that there is 1 packet between the FP result and its use. 4 5; CHECK: loop0([[LOOP0:.LBB[0-9_]+]], 6; CHECK: [[LOOP0]] 7; CHECK: [[REG0:(r[0-9]+)]] += sfmpy(r{{[0-9]+}},r{{[0-9]+}}) 8; CHECK: } 9; CHECK: } 10; CHECK: r{{[0-9]+}} = {{.*}}[[REG0]] 11 12; Function Attrs: nounwind readnone 13define void @f0(i32 %a0, i32 %a1) #0 { 14b0: 15 %v0 = alloca [1000 x float], align 64 16 %v1 = alloca [1000 x float], align 64 17 %v2 = alloca [1000 x float], align 64 18 %v3 = alloca [1000 x float], align 64 19 call void @llvm.lifetime.start.p0(i64 4000, ptr %v0) #2 20 call void @llvm.lifetime.start.p0(i64 4000, ptr %v1) #2 21 call void @llvm.lifetime.start.p0(i64 4000, ptr %v2) #2 22 call void @llvm.lifetime.start.p0(i64 4000, ptr %v3) #2 23 %v8 = icmp sgt i32 %a1, 0 24 %v9 = add i32 %a1, -1 25 br label %b1 26 27b1: ; preds = %b3, %b0 28 %v11 = phi i32 [ 0, %b0 ], [ %v34, %b3 ] 29 br i1 %v8, label %b2, label %b3 30 31b2: ; preds = %b2, %b1 32 %v12 = phi ptr [ %v33, %b2 ], [ %v3, %b1 ] 33 %v13 = phi i32 [ %v31, %b2 ], [ 0, %b1 ] 34 %v14 = mul nsw i32 %v13, %a1 35 %v15 = add nsw i32 %v14, %v11 36 %v16 = getelementptr inbounds [1000 x float], ptr %v1, i32 0, i32 %v15 37 %v17 = load float, ptr %v16, align 4, !tbaa !0 38 %v18 = fmul float %v17, %v17 39 %v19 = mul nsw i32 %v13, 25 40 %v20 = add nsw i32 %v19, %v11 41 %v21 = getelementptr inbounds [1000 x float], ptr %v2, i32 0, i32 %v20 42 %v22 = load float, ptr %v21, align 4, !tbaa !0 43 %v23 = fmul float %v22, %v22 44 %v24 = fadd float %v18, %v23 45 %v25 = load float, ptr %v12, align 4, !tbaa !0 46 %v26 = fmul float %v25, %v25 47 %v27 = fadd float %v24, %v26 48 %v28 = getelementptr inbounds [1000 x float], ptr %v0, i32 0, i32 %v20 49 %v29 = load float, ptr %v28, align 4, !tbaa !0 50 %v30 = fadd float %v29, %v27 51 store float %v30, ptr %v28, align 4, !tbaa !0 52 %v31 = add nuw nsw i32 %v13, 1 53 %v32 = icmp eq i32 %v13, %v9 54 %v33 = getelementptr float, ptr %v12, i32 1 55 br i1 %v32, label %b3, label %b2 56 57b3: ; preds = %b2, %b1 58 %v34 = add nuw nsw i32 %v11, 1 59 %v35 = icmp eq i32 %v34, 25 60 br i1 %v35, label %b4, label %b1 61 62b4: ; preds = %b3 63 call void @llvm.lifetime.end.p0(i64 4000, ptr %v3) #2 64 call void @llvm.lifetime.end.p0(i64 4000, ptr %v2) #2 65 call void @llvm.lifetime.end.p0(i64 4000, ptr %v1) #2 66 call void @llvm.lifetime.end.p0(i64 4000, ptr %v0) #2 67 ret void 68} 69 70; Function Attrs: argmemonly nounwind 71declare void @llvm.lifetime.start.p0(i64, ptr nocapture) #1 72 73; Function Attrs: argmemonly nounwind 74declare void @llvm.lifetime.end.p0(i64, ptr nocapture) #1 75 76attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 77attributes #1 = { argmemonly nounwind } 78attributes #2 = { nounwind } 79 80!0 = !{!1, !1, i64 0} 81!1 = !{!"float", !2, i64 0} 82!2 = !{!"omnipotent char", !3, i64 0} 83!3 = !{!"Simple C/C++ TBAA"} 84