xref: /llvm-project/llvm/test/CodeGen/Hexagon/float.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956)
1; RUN: llc -mtriple=hexagon < %s | FileCheck %s
2; CHECK: sfadd
3; CHECK: sfsub
4
5define void @f0(ptr %a0, float %a1, float %a2) #0 {
6b0:
7  %v0 = alloca ptr, align 4
8  %v1 = alloca float, align 4
9  %v2 = alloca float, align 4
10  store ptr %a0, ptr %v0, align 4
11  store float %a1, ptr %v1, align 4
12  store float %a2, ptr %v2, align 4
13  %v3 = load ptr, ptr %v0, align 4
14  %v4 = load float, ptr %v3
15  %v5 = load float, ptr %v1, align 4
16  %v6 = fadd float %v4, %v5
17  %v7 = load float, ptr %v2, align 4
18  %v8 = fsub float %v6, %v7
19  %v9 = load ptr, ptr %v0, align 4
20  store float %v8, ptr %v9
21  ret void
22}
23
24attributes #0 = { nounwind "target-cpu"="hexagonv5" }
25