1; RUN: llc -mtriple=hexagon < %s | FileCheck %s 2 3; CHECK: count_leading_0: 4; CHECK: cl0(r0) 5define i32 @count_leading_0(i32 %p) #0 { 6 %1 = call i32 @llvm.ctlz.i32(i32 %p, i1 false) 7 ret i32 %1 8} 9 10; CHECK: count_leading_0p: 11; CHECK: cl0(r1:0) 12define i32 @count_leading_0p(i64 %p) #0 { 13 %1 = call i64 @llvm.ctlz.i64(i64 %p, i1 false) 14 %2 = trunc i64 %1 to i32 15 ret i32 %2 16} 17 18; CHECK: count_leading_1: 19; CHECK: cl1(r0) 20define i32 @count_leading_1(i32 %p) #0 { 21 %1 = xor i32 %p, -1 22 %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false) 23 ret i32 %2 24} 25 26; CHECK: count_leading_1p: 27; CHECK: cl1(r1:0) 28define i32 @count_leading_1p(i64 %p) #0 { 29 %1 = xor i64 %p, -1 30 %2 = call i64 @llvm.ctlz.i64(i64 %1, i1 false) 31 %3 = trunc i64 %2 to i32 32 ret i32 %3 33} 34 35 36 37; CHECK: count_trailing_0: 38; CHECK: ct0(r0) 39define i32 @count_trailing_0(i32 %p) #0 { 40 %1 = call i32 @llvm.cttz.i32(i32 %p, i1 false) 41 ret i32 %1 42} 43 44; CHECK: count_trailing_0p: 45; CHECK: ct0(r1:0) 46define i32 @count_trailing_0p(i64 %p) #0 { 47 %1 = call i64 @llvm.cttz.i64(i64 %p, i1 false) 48 %2 = trunc i64 %1 to i32 49 ret i32 %2 50} 51 52; CHECK: count_trailing_1: 53; CHECK: ct1(r0) 54define i32 @count_trailing_1(i32 %p) #0 { 55 %1 = xor i32 %p, -1 56 %2 = call i32 @llvm.cttz.i32(i32 %1, i1 false) 57 ret i32 %2 58} 59 60; CHECK: count_trailing_1p: 61; CHECK: ct1(r1:0) 62define i32 @count_trailing_1p(i64 %p) #0 { 63 %1 = xor i64 %p, -1 64 %2 = call i64 @llvm.cttz.i64(i64 %1, i1 false) 65 %3 = trunc i64 %2 to i32 66 ret i32 %3 67} 68 69declare i32 @llvm.ctlz.i32(i32, i1) 70declare i64 @llvm.ctlz.i64(i64, i1) 71declare i32 @llvm.cttz.i32(i32, i1) 72declare i64 @llvm.cttz.i64(i64, i1) 73 74attributes #0 = { nounwind "target-cpu"="hexagonv55" } 75 76