1; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s 2 3; In DAG combiner, eliminate a store in cases where the store is fed by a 4; load from the same location. This is already done in cases where the store's 5; chain reaches the "output chain" of the load, this tests for cases where 6; the load's "input chain" is reached via an intervening node (eg. TokenFactor) 7; that ensures ordering. 8 9target triple = "hexagon" 10 11%s.0 = type { [3 x i32] } 12 13; Function Attrs: nounwind 14define void @f0(i32 %a0, i32 %a1, ptr nocapture %a2, ptr nocapture %a3) #0 { 15b0: 16; Pick one store that happens as a result. This isn't the best, but a regular 17; expression for a register name matches some unrelated load. 18; CHECK: %bb. 19; CHECK: = memw(r3+#8) 20; CHECK-NOT: memw(r3+#8) = 21; CHECK: %bb. 22 call void @llvm.memcpy.p0.p0.i32(ptr align 4 %a2, ptr align 4 %a3, i32 12, i1 false) 23 %v3 = zext i32 %a0 to i96 24 %v4 = load i96, ptr %a2, align 4 25 %v5 = shl nuw nsw i96 %v3, 48 26 %v6 = and i96 %v5, 281474976710656 27 %v7 = and i96 %v4, -281474976710657 28 %v8 = or i96 %v7, %v6 29 store i96 %v8, ptr %a2, align 4 30 %v9 = icmp eq i32 %a1, 2147483647 31 br i1 %v9, label %b1, label %b2 32 33b1: ; preds = %b0 34 %v10 = and i96 %v8, -12582913 35 br label %b3 36 37b2: ; preds = %b0 38 %v12 = load i96, ptr %a3, align 4 39 %v13 = trunc i96 %v12 to i32 40 %v14 = add i32 %v13, %a1 41 %v15 = zext i32 %v14 to i96 42 %v16 = and i96 %v15, 4194303 43 %v17 = and i96 %v8, -4194304 44 %v18 = or i96 %v16, %v17 45 store i96 %v18, ptr %a2, align 4 46 %v19 = load i96, ptr %a3, align 4 47 %v20 = and i96 %v19, 12582912 48 %v21 = and i96 %v18, -12582913 49 %v22 = or i96 %v21, %v20 50 br label %b3 51 52b3: ; preds = %b2, %b1 53 %v23 = phi i96 [ %v22, %b2 ], [ %v10, %b1 ] 54 store i96 %v23, ptr %a2, align 4 55 ret void 56} 57 58; Function Attrs: argmemonly nounwind 59declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture readonly, i32, i1) #1 60 61attributes #0 = { nounwind } 62attributes #1 = { argmemonly nounwind } 63