1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; RUN: llc -mtriple=hexagon < %s | FileCheck %s 3 4define i16 @popcount_i16(i16 %a0) #0 { 5; CHECK-LABEL: popcount_i16: 6; CHECK: .cfi_startproc 7; CHECK-NEXT: // %bb.0: 8; CHECK-NEXT: { 9; CHECK-NEXT: r1 = #0 10; CHECK-NEXT: r0 = zxth(r0) 11; CHECK-NEXT: } 12; CHECK-NEXT: { 13; CHECK-NEXT: r0 = popcount(r1:0) 14; CHECK-NEXT: jumpr r31 15; CHECK-NEXT: } 16 %v0 = tail call i16 @llvm.ctpop.i16(i16 %a0) #1 17 ret i16 %v0 18} 19 20define i32 @popcount_i32(i32 %a0) #0 { 21; CHECK-LABEL: popcount_i32: 22; CHECK: .cfi_startproc 23; CHECK-NEXT: // %bb.0: 24; CHECK-NEXT: { 25; CHECK-NEXT: r1 = #0 26; CHECK-NEXT: } 27; CHECK-NEXT: { 28; CHECK-NEXT: r0 = popcount(r1:0) 29; CHECK-NEXT: jumpr r31 30; CHECK-NEXT: } 31 %v0 = tail call i32 @llvm.ctpop.i32(i32 %a0) #1 32 ret i32 %v0 33} 34 35define i64 @popcount_i64(i64 %a0) #0 { 36; CHECK-LABEL: popcount_i64: 37; CHECK: .cfi_startproc 38; CHECK-NEXT: // %bb.0: 39; CHECK-NEXT: { 40; CHECK-NEXT: r0 = popcount(r1:0) 41; CHECK-NEXT: r1 = #0 42; CHECK-NEXT: jumpr r31 43; CHECK-NEXT: } 44 %v0 = tail call i64 @llvm.ctpop.i64(i64 %a0) #1 45 ret i64 %v0 46} 47 48define i16 @ctlz_i16(i16 %a0) #0 { 49; CHECK-LABEL: ctlz_i16: 50; CHECK: .cfi_startproc 51; CHECK-NEXT: // %bb.0: 52; CHECK-NEXT: { 53; CHECK-NEXT: r0 = aslh(r0) 54; CHECK-NEXT: } 55; CHECK-NEXT: { 56; CHECK-NEXT: r0 = cl0(r0) 57; CHECK-NEXT: jumpr r31 58; CHECK-NEXT: } 59 %v0 = tail call i16 @llvm.ctlz.i16(i16 %a0, i1 true) #1 60 ret i16 %v0 61} 62 63define i32 @ctlz_i32(i32 %a0) #0 { 64; CHECK-LABEL: ctlz_i32: 65; CHECK: .cfi_startproc 66; CHECK-NEXT: // %bb.0: 67; CHECK-NEXT: { 68; CHECK-NEXT: r0 = cl0(r0) 69; CHECK-NEXT: jumpr r31 70; CHECK-NEXT: } 71 %v0 = tail call i32 @llvm.ctlz.i32(i32 %a0, i1 true) #1 72 ret i32 %v0 73} 74 75define i64 @ctlz_i64(i64 %a0) #0 { 76; CHECK-LABEL: ctlz_i64: 77; CHECK: .cfi_startproc 78; CHECK-NEXT: // %bb.0: 79; CHECK-NEXT: { 80; CHECK-NEXT: r0 = cl0(r1:0) 81; CHECK-NEXT: r1 = #0 82; CHECK-NEXT: jumpr r31 83; CHECK-NEXT: } 84 %v0 = tail call i64 @llvm.ctlz.i64(i64 %a0, i1 true) #1 85 ret i64 %v0 86} 87 88define i16 @cttz_i16(i16 %a0) #0 { 89; CHECK-LABEL: cttz_i16: 90; CHECK: .cfi_startproc 91; CHECK-NEXT: // %bb.0: 92; CHECK-NEXT: { 93; CHECK-NEXT: r0 = ct0(r0) 94; CHECK-NEXT: jumpr r31 95; CHECK-NEXT: } 96 %v0 = tail call i16 @llvm.cttz.i16(i16 %a0, i1 true) #1 97 ret i16 %v0 98} 99 100define i32 @cttz_i32(i32 %a0) #0 { 101; CHECK-LABEL: cttz_i32: 102; CHECK: .cfi_startproc 103; CHECK-NEXT: // %bb.0: 104; CHECK-NEXT: { 105; CHECK-NEXT: r0 = ct0(r0) 106; CHECK-NEXT: jumpr r31 107; CHECK-NEXT: } 108 %v0 = tail call i32 @llvm.cttz.i32(i32 %a0, i1 true) #1 109 ret i32 %v0 110} 111 112define i64 @cttz_i64(i64 %a0) #0 { 113; CHECK-LABEL: cttz_i64: 114; CHECK: .cfi_startproc 115; CHECK-NEXT: // %bb.0: 116; CHECK-NEXT: { 117; CHECK-NEXT: r0 = ct0(r1:0) 118; CHECK-NEXT: r1 = #0 119; CHECK-NEXT: jumpr r31 120; CHECK-NEXT: } 121 %v0 = tail call i64 @llvm.cttz.i64(i64 %a0, i1 true) #1 122 ret i64 %v0 123} 124 125define i16 @bswap_i16(i16 %a0) #0 { 126; CHECK-LABEL: bswap_i16: 127; CHECK: .cfi_startproc 128; CHECK-NEXT: // %bb.0: 129; CHECK-NEXT: { 130; CHECK-NEXT: r0 = swiz(r0) 131; CHECK-NEXT: } 132; CHECK-NEXT: { 133; CHECK-NEXT: r0 = lsr(r0,#16) 134; CHECK-NEXT: jumpr r31 135; CHECK-NEXT: } 136 %v0 = tail call i16 @llvm.bswap.i16(i16 %a0) #1 137 ret i16 %v0 138} 139 140define i32 @bswap_i32(i32 %a0) #0 { 141; CHECK-LABEL: bswap_i32: 142; CHECK: .cfi_startproc 143; CHECK-NEXT: // %bb.0: 144; CHECK-NEXT: { 145; CHECK-NEXT: r0 = swiz(r0) 146; CHECK-NEXT: jumpr r31 147; CHECK-NEXT: } 148 %v0 = tail call i32 @llvm.bswap.i32(i32 %a0) #1 149 ret i32 %v0 150} 151 152define i64 @bswap_i64(i64 %a0) #0 { 153; CHECK-LABEL: bswap_i64: 154; CHECK: .cfi_startproc 155; CHECK-NEXT: // %bb.0: 156; CHECK-NEXT: { 157; CHECK-NEXT: r2 = swiz(r1) 158; CHECK-NEXT: r3 = swiz(r0) 159; CHECK-NEXT: } 160; CHECK-NEXT: { 161; CHECK-NEXT: r1:0 = combine(r3,r2) 162; CHECK-NEXT: jumpr r31 163; CHECK-NEXT: } 164 %v0 = tail call i64 @llvm.bswap.i64(i64 %a0) #1 165 ret i64 %v0 166} 167 168define <2 x i16> @bswap_v2i16(<2 x i16> %a0) #0 { 169; CHECK-LABEL: bswap_v2i16: 170; CHECK: .cfi_startproc 171; CHECK-NEXT: // %bb.0: 172; CHECK-NEXT: { 173; CHECK-NEXT: r0 = swiz(r0) 174; CHECK-NEXT: } 175; CHECK-NEXT: { 176; CHECK-NEXT: r0 = combine(r0.l,r0.h) 177; CHECK-NEXT: jumpr r31 178; CHECK-NEXT: } 179 %v0 = tail call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %a0) 180 ret <2 x i16> %v0 181} 182 183define <4 x i16> @bswap_v4i16(<4 x i16> %a0) #0 { 184; CHECK-LABEL: bswap_v4i16: 185; CHECK: .cfi_startproc 186; CHECK-NEXT: // %bb.0: 187; CHECK-NEXT: { 188; CHECK-NEXT: r3:2 = vlsrh(r1:0,#8) 189; CHECK-NEXT: r5:4 = vaslh(r1:0,#8) 190; CHECK-NEXT: } 191; CHECK-NEXT: { 192; CHECK-NEXT: r1:0 = or(r3:2,r5:4) 193; CHECK-NEXT: jumpr r31 194; CHECK-NEXT: } 195 %v0 = tail call <4 x i16> @llvm.bswap.v4i16(<4 x i16> %a0) 196 ret <4 x i16> %v0 197} 198 199define <2 x i32> @bswap_v2i32(<2 x i32> %a0) #0 { 200; CHECK-LABEL: bswap_v2i32: 201; CHECK: .cfi_startproc 202; CHECK-NEXT: // %bb.0: 203; CHECK-NEXT: { 204; CHECK-NEXT: r0 = swiz(r0) 205; CHECK-NEXT: r1 = swiz(r1) 206; CHECK-NEXT: } 207; CHECK-NEXT: { 208; CHECK-NEXT: jumpr r31 209; CHECK-NEXT: } 210 %v0 = tail call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %a0) 211 ret <2 x i32> %v0 212} 213 214define i16 @brev_i16(i16 %a0) #0 { 215; CHECK-LABEL: brev_i16: 216; CHECK: .cfi_startproc 217; CHECK-NEXT: // %bb.0: 218; CHECK-NEXT: { 219; CHECK-NEXT: r0 = brev(r0) 220; CHECK-NEXT: } 221; CHECK-NEXT: { 222; CHECK-NEXT: r0 = lsr(r0,#16) 223; CHECK-NEXT: jumpr r31 224; CHECK-NEXT: } 225 %v0 = tail call i16 @llvm.bitreverse.i16(i16 %a0) #1 226 ret i16 %v0 227} 228 229define i32 @brev_i32(i32 %a0) #0 { 230; CHECK-LABEL: brev_i32: 231; CHECK: .cfi_startproc 232; CHECK-NEXT: // %bb.0: 233; CHECK-NEXT: { 234; CHECK-NEXT: r0 = brev(r0) 235; CHECK-NEXT: jumpr r31 236; CHECK-NEXT: } 237 %v0 = tail call i32 @llvm.bitreverse.i32(i32 %a0) #1 238 ret i32 %v0 239} 240 241define i64 @brev_i64(i64 %a0) #0 { 242; CHECK-LABEL: brev_i64: 243; CHECK: .cfi_startproc 244; CHECK-NEXT: // %bb.0: 245; CHECK-NEXT: { 246; CHECK-NEXT: r1:0 = brev(r1:0) 247; CHECK-NEXT: jumpr r31 248; CHECK-NEXT: } 249 %v0 = tail call i64 @llvm.bitreverse.i64(i64 %a0) #1 250 ret i64 %v0 251} 252 253define <4 x i8> @brev_v4i8(<4 x i8> %a0) #0 { 254; CHECK-LABEL: brev_v4i8: 255; CHECK: .cfi_startproc 256; CHECK-NEXT: // %bb.0: 257; CHECK-NEXT: { 258; CHECK-NEXT: r0 = brev(r0) 259; CHECK-NEXT: } 260; CHECK-NEXT: { 261; CHECK-NEXT: r0 = swiz(r0) 262; CHECK-NEXT: jumpr r31 263; CHECK-NEXT: } 264 %v0 = tail call <4 x i8> @llvm.bitreverse.v4i8(<4 x i8> %a0) 265 ret <4 x i8> %v0 266} 267 268define <8 x i8> @brev_v8i8(<8 x i8> %a0) #0 { 269; CHECK-LABEL: brev_v8i8: 270; CHECK: .cfi_startproc 271; CHECK-NEXT: // %bb.0: 272; CHECK-NEXT: { 273; CHECK-NEXT: r3:2 = brev(r1:0) 274; CHECK-NEXT: } 275; CHECK-NEXT: { 276; CHECK-NEXT: r0 = swiz(r3) 277; CHECK-NEXT: r1 = swiz(r2) 278; CHECK-NEXT: } 279; CHECK-NEXT: { 280; CHECK-NEXT: jumpr r31 281; CHECK-NEXT: } 282 %v0 = tail call <8 x i8> @llvm.bitreverse.v8i8(<8 x i8> %a0) 283 ret <8 x i8> %v0 284} 285 286define <2 x i16> @brev_v2i16(<2 x i16> %a0) #0 { 287; CHECK-LABEL: brev_v2i16: 288; CHECK: .cfi_startproc 289; CHECK-NEXT: // %bb.0: 290; CHECK-NEXT: { 291; CHECK-NEXT: r0 = brev(r0) 292; CHECK-NEXT: } 293; CHECK-NEXT: { 294; CHECK-NEXT: r0 = combine(r0.l,r0.h) 295; CHECK-NEXT: jumpr r31 296; CHECK-NEXT: } 297 %v0 = tail call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a0) 298 ret <2 x i16> %v0 299} 300 301define <4 x i16> @brev_v4i16(<4 x i16> %a0) #0 { 302; CHECK-LABEL: brev_v4i16: 303; CHECK: .cfi_startproc 304; CHECK-NEXT: // %bb.0: 305; CHECK-NEXT: { 306; CHECK-NEXT: r3:2 = brev(r1:0) 307; CHECK-NEXT: } 308; CHECK-NEXT: { 309; CHECK-NEXT: r0 = combine(r3.l,r3.h) 310; CHECK-NEXT: jumpr r31 311; CHECK-NEXT: r1 = combine(r2.l,r2.h) 312; CHECK-NEXT: } 313 %v0 = tail call <4 x i16> @llvm.bitreverse.v4i16(<4 x i16> %a0) 314 ret <4 x i16> %v0 315} 316 317define <2 x i32> @brev_v2i32(<2 x i32> %a0) #0 { 318; CHECK-LABEL: brev_v2i32: 319; CHECK: .cfi_startproc 320; CHECK-NEXT: // %bb.0: 321; CHECK-NEXT: { 322; CHECK-NEXT: r3:2 = brev(r1:0) 323; CHECK-NEXT: } 324; CHECK-NEXT: { 325; CHECK-NEXT: r1:0 = combine(r2,r3) 326; CHECK-NEXT: jumpr r31 327; CHECK-NEXT: } 328 %v0 = tail call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %a0) 329 ret <2 x i32> %v0 330} 331 332 333declare i16 @llvm.ctpop.i16(i16) #1 334declare i32 @llvm.ctpop.i32(i32) #1 335declare i64 @llvm.ctpop.i64(i64) #1 336 337declare i16 @llvm.ctlz.i16(i16, i1) #1 338declare i32 @llvm.ctlz.i32(i32, i1) #1 339declare i64 @llvm.ctlz.i64(i64, i1) #1 340 341declare i16 @llvm.cttz.i16(i16, i1) #1 342declare i32 @llvm.cttz.i32(i32, i1) #1 343declare i64 @llvm.cttz.i64(i64, i1) #1 344 345declare i16 @llvm.bswap.i16(i16) #1 346declare i32 @llvm.bswap.i32(i32) #1 347declare i64 @llvm.bswap.i64(i64) #1 348 349declare <2 x i16> @llvm.bswap.v2i16(<2 x i16>) #1 350declare <4 x i16> @llvm.bswap.v4i16(<4 x i16>) #1 351declare <2 x i32> @llvm.bswap.v2i32(<2 x i32>) #1 352 353declare i16 @llvm.bitreverse.i16(i16) #1 354declare i32 @llvm.bitreverse.i32(i32) #1 355declare i64 @llvm.bitreverse.i64(i64) #1 356 357declare <4 x i8> @llvm.bitreverse.v4i8(<4 x i8>) #1 358declare <8 x i8> @llvm.bitreverse.v8i8(<8 x i8>) #1 359 360declare <2 x i16> @llvm.bitreverse.v2i16(<2 x i16>) #1 361declare <4 x i16> @llvm.bitreverse.v4i16(<4 x i16>) #1 362declare <2 x i32> @llvm.bitreverse.v2i32(<2 x i32>) #1 363 364 365attributes #0 = { "target-features"="+v68,-long-calls" } 366attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } 367 368