1; RUN: llc -mtriple=hexagon -hexbit-extract=0 < %s | FileCheck %s 2 3; Make sure we don't generate zxtb to transfer a predicate register into 4; a general purpose register. 5 6; CHECK: r0 = p0 7; CHECK-NOT: zxtb(p 8; CHECK-NOT: and(p 9; CHECK-NOT: extract(p 10; CHECK-NOT: extractu(p 11 12target triple = "hexagon" 13 14; Function Attrs: nounwind 15define i32 @fred() local_unnamed_addr #0 { 16entry: 17 %0 = tail call i32 @llvm.hexagon.C4.and.and(i32 undef, i32 undef, i32 undef) 18 ret i32 %0 19} 20 21declare i32 @llvm.hexagon.C4.and.and(i32, i32, i32) #1 22 23attributes #0 = { nounwind "target-cpu"="hexagonv5" } 24attributes #1 = { nounwind readnone } 25