xref: /llvm-project/llvm/test/CodeGen/Hexagon/bit-extract.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956)
1; RUN: llc -mtriple=hexagon < %s | FileCheck %s
2
3target triple = "hexagon"
4
5; CHECK-LABEL: ua
6; CHECK: extractu(r0,#26,#0)
7define i32 @ua(i32 %x) local_unnamed_addr #0 {
8entry:
9  %shl = and i32 %x, 67108863
10  ret i32 %shl
11}
12
13; CHECK-LABEL: ub
14; CHECK: extractu(r0,#16,#4)
15define i32 @ub(i32 %x) local_unnamed_addr #0 {
16entry:
17  %0 = lshr i32 %x, 4
18  %shr = and i32 %0, 65535
19  ret i32 %shr
20}
21
22; CHECK-LABEL: uc
23; CHECK: extractu(r0,#24,#0)
24define i32 @uc(i32 %x) local_unnamed_addr #0 {
25entry:
26  %shl = and i32 %x, 16777215
27  ret i32 %shl
28}
29
30; CHECK-LABEL: ud
31; CHECK: extractu(r0,#16,#8)
32define i32 @ud(i32 %x) local_unnamed_addr #0 {
33entry:
34  %bf.lshr = lshr i32 %x, 8
35  %bf.clear = and i32 %bf.lshr, 65535
36  ret i32 %bf.clear
37}
38
39; CHECK-LABEL: sa
40; CHECK: extract(r0,#26,#0)
41define i32 @sa(i32 %x) local_unnamed_addr #0 {
42entry:
43  %shl = shl i32 %x, 6
44  %shr = ashr exact i32 %shl, 6
45  ret i32 %shr
46}
47
48; CHECK-LABEL: sb
49; CHECK: extract(r0,#16,#4)
50define i32 @sb(i32 %x) local_unnamed_addr #0 {
51entry:
52  %shl = shl i32 %x, 12
53  %shr = ashr i32 %shl, 16
54  ret i32 %shr
55}
56
57; CHECK-LABEL: sc
58; CHECK: extract(r0,#24,#0)
59define i32 @sc(i32 %x) local_unnamed_addr #0 {
60entry:
61  %shl = shl i32 %x, 8
62  %shr = ashr exact i32 %shl, 8
63  ret i32 %shr
64}
65
66; CHECK-LABEL: sd
67; CHECK: extract(r0,#16,#8)
68define i32 @sd(i32 %x) local_unnamed_addr #0 {
69entry:
70  %bf.shl = shl i32 %x, 8
71  %bf.ashr = ashr i32 %bf.shl, 16
72  ret i32 %bf.ashr
73}
74
75attributes #0 = { noinline norecurse nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }
76