1; RUN: llc -mtriple=hexagon < %s | FileCheck %s 2 3target triple = "hexagon" 4 5; CHECK-LABEL: xh_sh 6; CHECK: sath 7; CHECK-NOT: sxth 8define i32 @xh_sh(i32 %x) local_unnamed_addr #0 { 9entry: 10 %0 = tail call i32 @llvm.hexagon.A2.sath(i32 %x) 11 %1 = tail call i32 @llvm.hexagon.A2.sxth(i32 %0) 12 ret i32 %1 13} 14 15; CHECK-LABEL: xb_sb 16; CHECK: satb 17; CHECK-NOT: sxtb 18define i32 @xb_sb(i32 %x) local_unnamed_addr #0 { 19entry: 20 %0 = tail call i32 @llvm.hexagon.A2.satb(i32 %x) 21 %1 = tail call i32 @llvm.hexagon.A2.sxtb(i32 %0) 22 ret i32 %1 23} 24 25; CHECK-LABEL: xuh_suh 26; CHECK: satuh 27; CHECK-NOT: zxth 28define i32 @xuh_suh(i32 %x) local_unnamed_addr #0 { 29entry: 30 %0 = tail call i32 @llvm.hexagon.A2.satuh(i32 %x) 31 %1 = tail call i32 @llvm.hexagon.A2.zxth(i32 %0) 32 ret i32 %1 33} 34 35; CHECK-LABEL: xub_sub 36; CHECK: satub 37; CHECK-NOT: zxtb 38define i32 @xub_sub(i32 %x) local_unnamed_addr #0 { 39entry: 40 %0 = tail call i32 @llvm.hexagon.A2.satub(i32 %x) 41 %1 = tail call i32 @llvm.hexagon.A2.zxtb(i32 %0) 42 ret i32 %1 43} 44 45 46declare i32 @llvm.hexagon.A2.sxtb(i32) #1 47declare i32 @llvm.hexagon.A2.sxth(i32) #1 48declare i32 @llvm.hexagon.A2.zxtb(i32) #1 49declare i32 @llvm.hexagon.A2.zxth(i32) #1 50 51declare i32 @llvm.hexagon.A2.satb(i32) #1 52declare i32 @llvm.hexagon.A2.sath(i32) #1 53declare i32 @llvm.hexagon.A2.satub(i32) #1 54declare i32 @llvm.hexagon.A2.satuh(i32) #1 55 56attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" } 57attributes #1 = { nounwind readnone } 58