xref: /llvm-project/llvm/test/CodeGen/Hexagon/base-offset-addr.ll (revision 2208c97c1bec2512d4e47b6223db6d95a7037956)
1; RUN: llc -mtriple=hexagon -enable-aa-sched-mi < %s
2; REQUIRES: asserts
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4; Make sure the base is a register and not an address.
5
6define fastcc void @Get_lsp_pol(ptr nocapture %f) #0 {
7entry:
8  %f5 = alloca i32, align 4
9  %arrayidx103 = getelementptr inbounds i32, ptr %f, i32 4
10  store i32 0, ptr %arrayidx103, align 4
11  %f5.0.load185 = load volatile i32, ptr %f5, align 4
12  ret void
13}
14
15attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
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