1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=hexagon < %s | FileCheck %s 3 4; Check that this compiles successfully. 5 6target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" 7target triple = "hexagon" 8 9@g0 = global <16 x i16> zeroinitializer, align 2 10 11define void @fred(<16 x i32> %a0, <16 x i32> %a1) #0 { 12; CHECK-LABEL: fred: 13; CHECK: // %bb.0: // %b0 14; CHECK-NEXT: { 15; CHECK-NEXT: r1:0 = combine(#-1,#32) 16; CHECK-NEXT: v2 = vxor(v2,v2) 17; CHECK-NEXT: q1 = vcmp.eq(v0.w,v1.w) 18; CHECK-NEXT: } 19; CHECK-NEXT: { 20; CHECK-NEXT: r7 = ##g0 21; CHECK-NEXT: q0 = vsetq(r0) 22; CHECK-NEXT: v0 = vmux(q1,v0,v2) 23; CHECK-NEXT: } 24; CHECK-NEXT: { 25; CHECK-NEXT: v30 = vand(q0,r1) 26; CHECK-NEXT: } 27; CHECK-NEXT: { 28; CHECK-NEXT: v0.h = vpacke(v0.w,v0.w) 29; CHECK-NEXT: } 30; CHECK-NEXT: { 31; CHECK-NEXT: v3 = vlalign(v2,v30,r7) 32; CHECK-NEXT: } 33; CHECK-NEXT: { 34; CHECK-NEXT: q2 = vand(v3,r1) 35; CHECK-NEXT: v1 = vlalign(v30,v2,r7) 36; CHECK-NEXT: } 37; CHECK-NEXT: { 38; CHECK-NEXT: q3 = vand(v1,r1) 39; CHECK-NEXT: v31 = vlalign(v2,v0,r7) 40; CHECK-NEXT: } 41; CHECK-NEXT: { 42; CHECK-NEXT: v0 = vlalign(v0,v2,r7) 43; CHECK-NEXT: if (q2) vmem(r7+#1) = v31 44; CHECK-NEXT: } 45; CHECK-NEXT: { 46; CHECK-NEXT: jumpr r31 47; CHECK-NEXT: if (q3) vmem(r7+#0) = v0 48; CHECK-NEXT: } 49b0: 50 %v0 = icmp eq <16 x i32> %a0, %a1 51 %v1 = select <16 x i1> %v0, <16 x i32> %a0, <16 x i32> zeroinitializer 52 %v2 = trunc <16 x i32> %v1 to <16 x i16> 53 store <16 x i16> %v2, ptr @g0, align 2 54 ret void 55} 56 57attributes #0 = { norecurse nounwind "target-cpu"="hexagonv65" "target-features"="+hvx-length64b,+hvxv65" } 58